EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 80
Universal Serial Bus (USB)
functions similar to a device controller, with added scheduling capability to control and initiate data traffic on the bus. The USB
2.0 embedded host includes the following features:
■ EHCI-like interface in high-speed mode (EHCI is the PC-based Enhanced Host Controller Interface)
■ OHCI-like interface in full- and low-speed modes (OHCI is the PC-based Open Host Controller Interface)
■ Support for point-to-point communications with one downstream port
■ Performance of all transaction scheduling in hardware
■ DMA adapter interface common to other FX3 peripherals
■ Fixed, one-to-one unidirectional endpoint to DMA socket mapping
■ Shared hardware endpoint managers (EPMs) among USB 2.0 device, USB 2.0 host, and USB 3.0 device controllers
6.4.5 USB OTG Controller
The FX3 USB subsystem is capable of supporting a USB 2.0 host, USB 2.0 peripheral, and a USB 3.0 peripheral. The FX3
OTG controller has global control of these functions. Dynamic role swapping is limited to USB 2.0 only by enabling the
appropriate USB 2.0 host or peripheral controller. The necessary control interface of the OTG controller facilitates:
■ Global control of the embedded host, and the USB 2.0 device function
■ Session Request Protocol (SRP) support per the OTG 2.0 specification
■ Host Negotiation Protocol (HNP) support per the OTG 2.0 specification
6.4.6 End-Point Memory
The end-point memory (EPM) supports data transfers through the USB 2.0 host controller, USB 2.0 function controller, and
USB 3.0 function controller blocks. It also supports the USB 3.0 bulk stream protocol. Two EPM units are available, dedicated
to each data direction.
6.4.7 DMA Adapters
The UIB has two dedicated DMA adapters that manage all DMA data flow in and out of the UIB block, one for each direction.
These DMA adapters are shared among the USB 3.0 device, USB 2.0 device, and USB 2.0 host controllers. Endpoint to DMA
socket mapping is fixed and unidirectional; that is, ingress endpoints 0 to 16 are mapped to UIB ingress DMA sockets 0 to 16,
and egress endpoints 0 to 16 are mapped to UIB DMA sockets 0 to 16. Hence the terms “socket” and “endpoint” are
interchangeable within the USB block. The DMA adapter is identical to those within other FX3 peripherals. Refer to the FX3
DMA Subsystem chapter on page 58 to learn how the FX3 DMA works.
6.4.8 USB I/O System
6.4.8.1 USB 2.0 OTG PHY
Within USB 2.0 subsystems, FX3 has a USB 2.0 transceiver with a UTMI+ interface to the back-end, multiplexed between the
USB 2.0 function and USB 2.0 embedded host controllers. It contains the required transceiver and OTG functionality,
including:
■ Standard four-wire signaling (VBUS, D+, D-, GND)
■ USB 2.0 High-/Full-/Low-Speed data transmission rate
■ USB 2.0 test modes fully supported
■ VBUS sensing for connection detection
■ Sampling of the USB_ID input for detection of A-device or B-device connection
■ Charging and discharging of DP line for starting a session as B-device
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