Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 402
DEV_EPO_CS
0xE0031498
10.11.8 DEV_EPO_CS
OUT Endpoint Control and Status Register
There are 16 DEV_EPO_CS registers. The address of each is calculated as DEV_EPO_CS(x) = 0xE0031498 + (x*0x4).
Hence DEV_EPO_CS(0) is at address 0xE0031498, DEV_EPO_CS(1) is at address 0xE0031498 + 0x4 and so on. The defi-
nition of each of these is the same.
Endpoint OUT Control and Status:
■ Set up USB Package buffering, ISO/BULK/INT, IN/OUT and enable/disable endpoint
■ Power up default the payload is 64-byte (Max payload count for Full Speed). In High Speed, the payload can be up to 512
for BULK and 1024 for ISO.
31 ISOERR_MASK Interrupt mask for ISOERR bit
30 SHORT_MASK Interrupt mask for SHORT bit
29 ZERO_MASK Interrupt mask for ZERO bit
28 DONE_MASK Interrupt mask for DONE bit
27 BNAK_MASK Interrupt mask for BNAK bit
26 COMMIT_MASK Interrupt mask for COMMIT bit
continued on next page
DEV_EPO_CS OUT Endpoint Control and Status Register 0xE0031498
b31 b30 b29 b28 b27 b26 b25 b24
ISOERR_MASK SHORT_MASK ZERO_MASK DONE_MASK BNAK_MASK COMMIT_MASK OVF_MASK
R/W R/W R/W R/W R/W R/W R/W
RRRRRRR
0000000
DEV_EPO_CS OUT Endpoint Control and Status Register
b23 b22 b21 b20 b19 b18 b17 b16
ISOERR SHORT ZERO DONE BNAK COMMIT OVF STALL
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W
R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R
00000000
DEV_EPO_CS OUT Endpoint Control and Status Register
b15 b14 b13 b12 b11 b10 b9 b8
NAK VALID ISOINPKS[1:0] TYPE[1:0] PAYLOAD[9:8]
R/W R/W R/W R/W R/W R/W R/W R/W
RRRRRRRR
010000
DEV_EPO_CS OUT Endpoint Control and Status Register
b7 b6 b5 b4 b3 b2 b1 b0
PAYLOAD[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W
RRRRRRRR
0x40
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English