Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 576
SPI_CONFIG
0xE0000C00
10.21 SPI Registers
10.21.1 SPI_CONFIG
SPI Configuration and Modes Register
Various modes of the SPI block.
31 ENABLE Enable block here, but only after all the configuration is set. Do not set this bit to 1 while changing any
other value in this register. This bit will be synchronized to the core clock.
Setting this bit to 0 will complete transmission of current sample. When DMA_MODE=1 any remain-
ing samples in the pipeline are discarded. When DMA_MODE=0 no samples are lost.
30 TX_CLEAR Use only when ENABLE=0; behavior undefined when ENABLE=1
0 Do nothing
1 Clear transmit FIFO
(After TX_CLEAR is set, software must wait for TX_DONE before clearing it)
29 RX_CLEAR Use only when ENABLE=0; behavior undefined when ENABLE=1
0 Do nothing
1 Clear receive FIFO
(Software must wait for RX_DATA=0 before clearing this bit again)
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SPI_CONFIG SPI Configuration and Modes Register 0xE0000C00
b31 b30 b29 b28 b27 b26 b25 b24
ENABLE TX_CLEAR RX_CLEAR
R/W R/W R/W
RRR
000
SPI_CONFIG SPI Configuration and Modes Register
b23 b22 b21 b20 b19 b18 b17 b16
DESELECT WL[5:0] SSPOL
R/W R/W R/W R/W R/W R/W R/W R/W
RRRRRRRR
080
SPI_CONFIG SPI Configuration and Modes Register
b15 b14 b13 b12 b11 b10 b9 b8
LAG[1:0] LEAD[1:0] CHPA CPOL SSNCTRL[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W
RRRRRRRR
11001
SPI_CONFIG SPI Configuration and Modes Register
b7 b6 b5 b4 b3 b2 b1 b0
LOOPBACK SSN_BIT ENDIAN DMA_MODE TX_ENABLE RX_ENABLE
R/W R/W R/W R/W R/W R/W
RRRRRR
000010
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English