EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 577
SPI_CONFIG
0xE0000C00
10.21.1 SPI_CONFIG (continued)
23 DESELECT 0 Normal SSN behavior.
1 Never assert SSN. Used to direct SPI traffic to non-default slaves whose SSN are con-
nected to GPIO.
22:17 WL[5:0] SPI transaction-unit length from 4 to 32 bits. 0-3 reserved.
16 SSPOL 0 SSN is active low, else active high.
15:14 LAG[1:0] SCK-SSN lag time. Indicates the number of half-clock cycles for which SSN needs to remain
asserted after the last SCK cycle including zero.
Note that LAG must be >0 when CHPA=1.
13:12 LEAD[1:0] SSN-SCK lead time.Encodings are: 0, 0.5, 1 or 1.5 SCK cycles. Indicates the number of half-clock
cycles SSN need to assert ahead of the first SCK cycle. However zero lead is not supported.
11 CPHA Transaction start mode. See section 3.2.2.2
10 CPOL 0 SCK idles low
1 SCK idles high
9:8 SSNCTRL[1:0] 00 SSN is toggled by firmware.
01 SSN remains asserted between each 8-bit transfer.
10 SSN asserts high at the end of the transfer.
11 SSN is governed by CPHA
5 LOOPBACK 0 No effect
1 Send the value being transmitted to the receive buffer. Disable external transmit and
receive.
4 SSN_BIT This bit controls SSN behavior at the end of each received and transmitted “byte” if SSNCTRL indi-
cate firmware SSN control. This bit is transmitted over SSN line *as is* and without regards to how
many cycles it is going out. SSPOL is applied. The firmware is expected to send one word at a time in
this mode. DESELECT bit takes precedence over this bit.
Typically the firmware will keep this bit asserted for the entire transaction that can span multiple
words. If SSN needs to be de-asserted between words, only single word transfers are possible when
SSN is under firmware control.
Modify only when ENABLE=0.
3 ENDIAN 0 MSB First
1 LSB First
2DMA_MODE 0 Register-based transfers
1 DMA-based transfers
1 TX_ENABLE 0 Transmitter disable, do not transmit data
1 Transmitter enabled
0 RX_ENABLE 0 Receiver disabled, ignore incoming data
1 Receive enabled
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