Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 263
GCTL_GPIO_FAST_CLK
0xE0052018
10.4.15 GCTL_GPIO_FAST_CLK
GPIO Fast Clock Configuration Register
31 CLK_EN Enable clock divider. Both the divider itself and its output are gated.
8:7 SIMPLE[1:0] Divider value for simple GPIOs relative to fast GPIO clock
0 Divide by 2
1 Divide by 4
2 Divide by 16
3 Divide by 64
6:5 SRC[1:0] Clock source select. This field selects between one of the following four prestage system clocks:
00 sys16_clk (sys_clk_pll divided by 16)
01 sys4_clk (sys_clk_pll divided by 4)
10 sys2_clk (sys_clk_pll divided by 2)
11 sys_clk_pll
4 HALFDIV Nonintegral divider select. This field adds 0.5 to the divider value selected by the DIV field. This yields
divider values from 2.5 to 16.5.
Note Do not use HALFDIV for FAST_CLK unless neither GPIO_SLOW_CLK or GPIO_SIMPLE_CLK
is used. They will not function with HALFDIV = 1.
Note Do not change HALFDIV after CLK_EN is set to 1 at least once, without first applying a hard-
ware reset. It can be set together with CLK_EN in a single register write.
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GCTL_GPIO_FAST_CLK GPIO Fast Clock Configuration Register 0xE0052018
b31 b30 b29 b28 b27 b26 b25 b24
CLK_EN
R/W
R
0
GCTL_GPIO_FAST_CLK GPIO Fast Clock Configuration Register
b23 b22 b21 b20 b19 b18 b17 b16
GCTL_GPIO_FAST_CLK GPIO Fast Clock Configuration Register
b15 b14 b13 b12 b11 b10 b9 b8
SIMPLE1
R/W
R
GCTL_GPIO_FAST_CLK GPIO Fast Clock Configuration Register
b7 b6 b5 b4 b3 b2 b1 b0
SIMPLE0
SRC[1:0] HALFDIV DIV[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W
R R R R R R R R
2000
1
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English