EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 51
4. Global Controller (GCTL)
The FX3 Global Controller (GCTL) supports I/O configuration, clock management, power management, and watchdog timer
configuration. The GCTL features include the following:
â– Can generate up to 500-MHz master clock
â– Serves as a clock source for various peripherals (such as UIB, PIB, and LPP) in FX3
â– Supports simple and complex GPIO configuration
â– Supports special function (such as SPI and GPIF II) I/O configuration
â– Supports watchdog timer configuration
â– Supports power mode control and various wakeup source configuration
4.1 GPIO Pins
All 60 GPIO pins in FX3 can function as GPIOs. Each is multiplexed to support other functions/peripheral blocks (such as
UART, SPI, and so on). By default, the pins are allocated in groups to either one function block or the other, depending on the
interface mode, in their respective power domains. In a typical application, all FX3 peripheral blocks are not used. Also, not all
pins of the blocks being used are utilized. Unused pins in each block may be overridden as simple or complex GPIO pins on
a pin-by-pin basis.
Simple GPIOs provide software-controlled and observable input and output capability only. In addition, they can also raise
interrupts. Complex GPIOs add three timer/counter registers for each group and support a variety of time-based functions.
They work off a slow or fast clock. Complex GPIOs can also be used as general-purpose timers by the firmware. There are
eight complex I/O pin groups, the elements of which are chosen in a modulo 8 fashion (complex I/O group 0: GPIO 0, 8, 16;
complex I/O group 1: GPIO 1, 9, 17, and so on). Each group can have different complex I/O functions (such as PWM, one
shot, and so on). However, only one pin from a group can use the complex I/O functions. The rest of the pins in the group are
used as block I/O or simple GPIO. Refer to Table 7 in the
EZ-USB FX3 datasheet for the GPIO configuration options.
4.1.1 I/O Matrix Configuration
I/O matrix configuration is used to configure the interface mode for I/O pins. The GCTL_IOMATRIX register must be config-
ured before accessing any alternate function pins. Table 4-1 lists the I/O pin alternate functions.
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