EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 177
Low Performance Peripherals (LPP)
The FX3 SPI block can share its MOSI, MISO, and SCLK pins with more than one slave connected to the SPI bus. In this
case, the SSN signal of the block cannot be used, and the multiple slave select signals need to be managed using GPIOs.
8.3.3 FX3 SPI Operations Overview
This section explains SPI operations.
8.3.3.1 Reset and Initialization
■ On reset, the SPI core is placed in a disabled state. The core becomes operational only after the firmware sets the
ENABLE bit in the configuration register of this block (SPI_CONFIG).
■ SPI clock speed is set in the GCTL block as is the case for all FX3 blocks. GCTL_SPI_CORE_CLK is used for setting the
SPI clock speed.
■ Once the block is reset, the firmware monitors the ACTIVE bit of the SPI_POWER register before accessing any of the
SPI block registers. The block ENABLE bit of SPI_CONFIG can be set only after the block is in the active state.
8.3.3.2 Modes Governing Transfers
The CPHA bit in the configuration register determines how a transfer starts.
1. CPHA=0: When CPHA=0, the slave starts monitoring the SCK line. The master first drives the data on the bus and then
toggles the clock to the active state.. The slave samples the data as soon as it detects the idle-to-active clock edge. The
master drives new data on the active-to-idle clock edge. Transfer ends when 8 bytes are transferred or aborts early by
deassertion of SSN signal from the master. When the SSN toggle mode is CPHA controlled as indicated by the SSNC-
TRL[1:0] bits, SSN returns to idle at the end of the transfer and asserts to begin a transfer.
2. CPHA=1: When CPHA=1, the master drives data on the idle-to-active clock edge, and the slave samples data on the
active-to-idle clock edge. Transfer ends when the word is transferred or aborts early by deassertion of SSN signal from
the master. When the SSN toggle mode is CPHA controlled as indicated by the SSNCTRL[1:0] bits, SSN can remain
asserted for multiple transfers when CPHA=1.
The CPOL bit defines the clock polarity. CPOL=0 means that the SCK is idle low. So the idle-to-active edge in this case is
the positive edge. The CPOL and CHPA bits need to be identical in all the devices connected to the SPI bus to ensure that
the data is sampled half a clock cycle after it is driven on the SPI bus.
8.3.4 SSN Control Configurations
At the beginning of a transfer, SCK is in idle and SSN is deasserted. SSN needs to be asserted (SSN=0) for the slave to begin
monitoring the SCK signal. SCK is driven by the SPI master only when data is being transferred. Conversely, when SCK
toggles, the status of the MISO line is interpreted as data when the RX mode is enabled. Once the TX mode is enabled, it is
the responsibility of the DMA producer to have data available, or SCK will go to idle. If the SPI block is configured to operate
in register mode, the SPI block expects to receive data if there is space in the RX register and transmits data if it exists in the
TX register. If any of these conditions are met, the SCK will not go to idle. If both are not met, then the SCK will go to idle.
The FX3 SPI supports a firmware-controlled SSN bit. When this mode is enabled, the value will be transmitted as is, except
when the DESELECT bit is set high, forcing slave deselecting. The firmware is entirely responsible for managing the polarity
and timing of this bit. When SSN is firmware controlled, there is no restriction on the DMA size. The firmware asserts the
SSN_BIT of SPI_CONFIG, and the SSN_BIT value will hold for the entire duration of the DMA transfer (as is the case with the
SPI EEPROM, where SSN remains asserted throughout). Upon completion of the transfer, the firmware can choose to
deassert SSN_BIT or leave it asserted. SSN is asserted for the entire multiword transaction.
The SPI block supports various lead and lag times between SSN and SCK as specified in the SPI_CONFIG register. the lead
of 0 is not supported. When the block is disabled, it must finish RX/TX of the current word.
When multiple slaves are connected to the SPI block, the SPI block handles SSN assertion for the default slave, and GPIO
lines handle SSN assertion for the other slaves under firmware control (The “default slave” is the one whose chip select is
connected to the FX3 SS# output pin). The DESELCT bit in SPI_CONFIG has to be set while accessing nondefault slaves,
logically disconnecting the default slave. The firmware can assert and deassert the GPIO line to select alternate slaves.
To Next Page
Loading...
Need help?
General
