Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 300
PIB_POWER
0xE0017F04
10.6.13 PIB_POWER
Power, Clock, and Reset Control Register
Every IP block implements a few MMIO registers at offset 0 in its MMIO to space that identify the block and control its power/
clock/reset state. These registers are located in the CPU/Interconnect power and clock domains and are accessible even
when power/clock of the block is switched off.
31 RESETN Active low reset signal for all logic in the block. Note that reset is active on all flops in the block when
either system reset is asserted (RESET# pin or SYSTEM_POWER.RESETN is asserted) or this sig-
nal is active.
After setting this bit to 1, firmware polls and waits for the ‘active’ bit to assert. Reading ‘1’ from ‘resetn’
does not indicate the block is out of reset. This may take some time depending on initialization tasks
and clock frequencies.
0 ACTIVE For blocks that must perform initialization after reset before becoming operational, this signal will
remain deasserted until initialization is complete. In other words, reading ACTIVE = 1 indicates that
the block is initialized and ready for operation.
PIB_POWER Power, Clock, and Reset Control Register 0xE0017F04
b31 b30 b29 b28 b27 b26 b25 b24
RESETN
R/W
R
0
PIB_RD_THRESHOLD Read Threshold Register
b23 b22 b21 b20 b19 b18 b17 b16
PIB_RD_THRESHOLD Read Threshold Register
b15 b14 b13 b12 b11 b10 b9 b8
PIB_RD_THRESHOLD Read Threshold Register
b7 b6 b5 b4 b3 b2 b1 b0
ACTIVE
R
W
0
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English