EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 184
Low Performance Peripherals (LPP)
8.7 FX3 UART Operations Overview
The FX3 architecture supports register-based UART operations for small transfers and DMA-based UART operations for
larger transfers. This section explains the UART operations.
8.7.1 Reset and Initialization
â– Upon reset, the UART block is placed in a disabled state. The UART block becomes operational when firmware sets the
ENABLE bit in the configuration register (UART_CONFIG).
â– UART clock speed is set in the GCTL block as is the case for all FX3 blocks. GCTL_UART_CORE_CLK is used to set the
UART clock speed. The UART core clock must be running at 16 times the frequency at the external interface (for exam-
ple, for a 100-kHz UART clock, the UART core clock is set to 1.6 MHz). This is required to generate the external clock with
the proper setup and hold with respect to the data.
â– Once the block is reset, firmware monitors the ACTIVE bit in the UART_POWER register before accessing any of the
UART block registers. Also, the block ENABLE bit of the UART_CONFIG register can be set only after the block is in the
active state.
8.7.2 Programming Model
The UART programming model is similar to I2C except for the control phase. No control phase is required in a UART, so only
the data phase exists. Data transfers can be either register based or DMA based.
8.7.3 Register-Based Transfers
ARM registers that convey core data to the data from the core and transmit it onto the bus are called EGRESS_DATA
registers. The set of registers used for receiving the data from the bus are called INGRESS_DATA registers. The firmware
can be notified of completion by interrupt or by polling through the status register.
4-byte-deep FIFOs hold egress and ingress data in their register spaces. Based on the status of FIFOs TX_SPACE,
TX_HALF, TX_DONE and RX_DATA, RX_HALF flags are asserted in the UART_STATUS and UART_INTR registers.
Firmware monitors these flags to perform data transfers.
The firmware can clear the FIFOs by asserting TX_CLEAR and RX_CLEAR bits in the UART_CONFIG register. Table 8-3
shows the conditions for the assertion of flags:
Table 8-3. Conditions for Assertion of Flags
8.7.3.1 DMA-Based Transfers
DMA based transfers use the UART sockets. The DMA interface supports sockets that are used to move the data between
the peripheral and the USB 3.0 interconnect. The sockets used for transmitting the data to the bus are called egress sockets.
The DMA sockets that are used for receiving the data from the bus (over the RX line) are called ingress sockets. Ingress and
egress sockets can be programmed to interrupt the CPU upon transaction completion. The transceiver always raises
interrupts in error conditions.
There are two separate BYTE_COUNT registers for the RX and TX paths. These two registers can be used only for DMA
mode and not for register mode transfers. The UART_TX_BYTE_COUNT register specifies the number of bytes to be written
out during DMA transfer. The UART_RX_BYTE_COUNT register is used to read the number of bytes received. Register
mode transfers are always treated as infinite-length transfers.
FLAG Asserted Egress FIFO State Ingress FIFO State
TX_SPACE Not full -
TX_HALF At least half empty -
TX_DONE Full -
RX_DATA - Not empty
RX_HALF - At least half full
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