Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 44
3. Memory and System Interconnect
The memory subsystem on the FX3 device comprises the system RAM that forms the main memory, SRAM controller, and
AHB-based interconnect that allows the ARM CPU and the hardware blocks to access these memories. The MMIO
interconnect provides access to registers in various peripheral blocks.
Because USB data moves through the system RAM (where USB endpoint buffers are implemented), FX3 implements a
specialized memory controller to arbitrate between the various types of traffic with high throughput and predictable latency.
Details on the arbitration mechanism and priorities are provided in System Interconnect on page 47.
3.1 Features
The FX3 memory and system interconnect supports the following:
■ 512 KB or 256 KB of system memory, depending on the FX3 part number selected
■ 16 KB of Instruction Tightly Couple Memory (I-TCM) and 8 KB of Data Tightly Couple Memory (D-TCM).
■ DMA architecture that can deliver 800 MBps bandwidth to memory
■ MMIO register access from CPU at up to 50 MBps (12.5 million 32-bit register accesses per second)
■ Guaranteed and bounded memory access latency for both CPU and DMA accesses
3.2 Block Diagram
Figure 3-1 shows a block diagram of the memory and system interconnect on the FX3 device.

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English