Cypress EZ-USB FX3 User Manual

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 283
PIB_INTR
0xE0010004
10.6.2 PIB_INTR
PIB Interrupt Request Register
The PIB_INTR and PIB_INTR_MASK registers control the interrupt behavior of the P-Port to the FX3 CPU. PIB_INTR indi-
cates interrupt cause, and PIB_INTR_MASK masks the causes that may assert INTR. These interrupts represent the P-Port
specific interrupts. The DMA adapter for P-Port has a number of socket-related interrupt causes that are outlined in the FX3
DMA Subsystem chapter on page 58.
31 GPIF_ERR An error occurred in the GPIF. Firmware clears this bit after handling the error. The error code is indi-
cated in PIB_ERROR.GPIF_ERR_CODE.
29 PIB_ERR The socket-based link controller encountered an error and needs attention. Firmware clears this bit
after handling the error. The error code is indicated in PIB_ERROR.PIB_ERR_CODE.
10 RD_THRESHOLD Indicates that AP has written to PP_RD_THRESHOLD register.
9 WR_THRESHOLD Indicates that AP has written to PP_WR_THRESHOLD register.
8 CONFIG_CHANGE AP has written a new value into PP_CONFIG.
7CLOCK_LOST PIB_CLK is no longer present. See PIB_CLOCK_DETECT for more details.
continued on next page
PIB_INTR PIB Interrupt Request Register 0xE0010004
b31 b30 b29 b28 b27 b26 b25 b24
GPIF_ERR PIB_ERR
R/W1C R/W1C
W1S W1S
0 0
PIB_INTR PIB Interrupt Request Register
b23 b22 b21 b20 b19 b18 b17 b16
PIB_INTR PIB Interrupt Request Register
b15 b14 b13 b12 b11 b10 b9 b8
RD_THRESHOLD WR_THRESHOLD CONFIG_CHANGE
R/W1C R/W1C R/W1C
W1S W1S W1S
000
PIB_INTR PIB Interrupt Request Register
b7 b6 b5 b4 b3 b2 b1 b0
CLOCK_LOST DLL_LOST_LOCK DLL_LOCKED GPIF_INTERRUPT WR_MB_FULL RD_MB_EMPTY
R/W1C R/W1C R/W1C R R/W1C R/W1C
W1S W1S W1S W
R/W1S R/W1S
0000
00
Bit Name Description

Cypress EZ-USB FX3 Specifications

General

Brand	Cypress
Model	EZ-USB FX3
Category	Controller
Language	English