EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 37
FX3 CPU Subsystem
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup SYS stack pointer */
mov r10, #0 /* Clear SYS mode sl */
mov r11, #0 /* Clear SYS fp */
ldr r2, =FX3_ABT_STACK_SIZE /* Pickup stack size */
mov r3, #ARM_ABT_MODE /* Build ABT mode CPSR */
msr CPSR_cxsf, r3 /* Enter ABT mode */
add r1, r1, r2 /* Calculate start of ABT stack */
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup ABT stack pointer */
mov r10, #0 /* Clear ABT mode sl */
mov r11, #0 /* Clear ABT fp */
ldr r2, =FX3_UND_STACK_SIZE /* Pickup stack size */
mov r3, #ARM_UND_MODE /* Build UND mode CPSR */
msr CPSR_cxsf, r3 /* Enter UND mode */
add r1, r1, r2 /* Calculate start of UND stack */
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup UND stack pointer */
mov r10, #0 /* Clear UND mode sl */
mov r11, #0 /* Clear UND fp */
ldr r2, =FX3_FIQ_STACK_SIZE /* Pickup stack size */
mov r0, #ARM_FIQ_MODE /* Build FIQ mode CPSR */
msr CPSR_c, r0 /* Enter FIQ mode */
add r1, r1, r2 /* Calculate start of FIQ stack */
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup FIQ stack pointer */
mov sl, #0 /* Clear sl */
mov fp, #0 /* Clear fp */
ldr r2, =FX3_IRQ_STACK_SIZE /* Pickup IRQ stack size */
mov r0, #ARM_IRQ_MODE /* Build IRQ mode CPSR */
msr CPSR_c, r0 /* Enter IRQ mode */
add r1, r1, r2 /* Calculate start of IRQ stack */
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup IRQ stack pointer */
ldr r2, =FX3_SVC_STACK_SIZE /* Pickup System stack size */
mov r0, #ARM_SVC_MODE /* Build SVC mode CPSR */
msr CPSR_c, r0 /* Enter SVC mode */
add r1, r1, r2 /* Calculate start of SVC stack */
bic r1, r1, #7 /* Ensure 8-byte alignment */
mov sp, r1 /* Setup SVC stack pointer */
Hint: The 8-KB D-TCM region can be used for the run-time stack regions if there is no other performance-critical data that
needs to be placed there.
2.3.1.2 Processor Registers
Table 2-2 shows the registers provided by the ARM9 processor core. The CPSR register is used to switch between various
processor modes.