EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 57
Global Controller (GCTL)
4.3.2 Power Modes
At any instant, FX3 is in one of the four power modes: normal, suspend, standby, or core power down. When FX3 is actively
executing its tasks, the system is in normal mode. The clock gating techniques in peripherals minimize the overall power con-
sumption.
On detecting prolonged periods of inactivity, the firmware can place FX3 in suspend mode. All ongoing port (peripheral) activ-
ities/transfers are completed, ports are disabled, and wakeup sources are set before entering the suspend state. In applica-
tions involving USB 3.0, the USB3 PHY is forced into the U3 state. USB2PHY, if used, is forced into suspend. The system
RAM transitions to a low-power mode in which read and write to RAM cannot be performed. The CPU is forced into the halt
state. The ARM core retains its state, including its program counter. All clocks except the 32-kHz standby are turned off by
disabling the system PLL through the global configuration block. In the absence of clocks, the I/O pins can be frozen to retain
their state as long as the I/O power domain is not turned off The INT# pin can be configured to indicate the presence of FX3
in low-power mode.
Further reduction in power is achieved by having the firmware place FX3 into the standby state, where in addition to disabling
clocks, the core power domain is turned off. As in suspend mode, the I/O states of powered peripheral I/O domains are frozen
and the ports are disabled. The essential configuration registers of logic blocks are first saved to the system RAM. Then the
system RAM itself is forced into the low-power memory retention only mode. The warm boot setting is enabled in the global
configuration block. Finally, the core is powered down. When FX3 comes out of standby, the CPU goes through a reset; the
bootloader senses the warm boot mode and restores the system to its original state after reloading the configuration values
(including the firmware resume point) from the system RAM.
Optionally, FX3 can be placed in core powered-down mode from standby mode, which also involves removing power from the
VDD pins. The contents of system SRAM are lost, and I/O pins retain their states, if suitably configured in the firmware. When
power is reapplied to the VDD pins, FX3 performs the normal power-on reset (POR) sequence.
4.3.3 Reset
Resets in FX3 are classified into two categories: hard reset and soft reset.
4.3.4 Hard Reset
A POR or a Reset# pin assertion initiates a hard reset. This sets all register bits to their default states and restarts the pro-
gram but retains the states of all register bits.
4.3.5 Soft Reset
A soft reset is generated by setting the appropriate bits in the GCTL_CONTROL register. There are two types of soft resets:
CPU reset and whole device reset.
â– CPU resets the CPU program counter. The firmware does not need to be reloaded following a CPU reset.
â– Whole device reset is identical to hard reset. The firmware must be reloaded following a whole device reset.
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