EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 41
FX3 CPU Subsystem
Table 2-4. FX3 Interrupt Sources
You can configure any of the 32 interrupt sources as fast interrupt request (FIQ), which takes the highest priority among the
interrupts. The rest of the interrupts are prioritized by user code through the VIC_VECT_PRIORITY registers. If two or more
interrupts are programmed with the same priority value, the source with the lower vector number assumes the higher priority.
The PL192 controller allows each of the interrupt sources to be independently masked (disabled) or unmasked (enabled) and
provides registers that report the raw interrupt status and the interrupt status after masking. The vector addresses for various
interrupt sources are programmed through the VIC_VEC_ADDRESS registers. When one or more interrupt sources are
active, the controller identifies the highest priority interrupt, stores the corresponding vector address in the VIC_ADDRESS
register, and then asserts the nIRQ signal to interrupt the ARM CPU.
Refer to Vectored Interrupt Controller (VIC) Registers on page 230 on for information about the various configuration and
status registers associated with the VIC.
Some interrupts in the FX3 system need to be prioritized over others to ensure that the application can meet all the USB spec
requirements and transfer rates. In particular, the USB core interrupt must be handled at the highest priority (can be selected
as FIQ), and all the DMA interrupts should be allotted the next high priority level.
To enable a specific interrupt source, the firmware has to do the following:
â– Point the VIC_VEC_ADDRESS register to the ISR.
Vector
Number
Interrupt Source Description Comments
0 GCTL_CORE
Interrupt raised on FX3 waking up from suspend or standby
low-power modes.
1 SW_INTR Software interrupt
This is a custom implementation of the software
interrupt scheme.
2 UNUSED Do not enable.
3 UNUSED Do not enable.
4 WATCHDOG_TIMER
Watchdog timer interrupt; the watchdog timer functions on
the basis of a 32-kHz clock signal with a user-configured
period
This is commonly used for OS scheduling on the
FX3 device.
5 UNUSED Do not enable.
6 GPIF_DMA DMA socket interrupt from the GPIF block
7 GPIF_CORE
General-purpose GPIF interrupts; indicates conditions such
as state machine interrupt, GPIF errors, mailbox register
access, and so on
8 USB_DMA DMA socket interrupt from the USB block
Applies to both USB device and host mode opera-
tion.
9 USB_CORE
General-purpose USB interrupts; indicates various condi-
tions triggered during device or host operation of the USB
block
10 UNUSED Do not enable.
11 STORAGE_DMA DMA socket interrupt from the storage (SD/MMC) interface Applies only to the FX3Sâ„¢ devices.
12 STORAGE0_CORE General-purpose interrupt from storage interface 0 Applies only to the FX3Sâ„¢ devices.
13 STORAGE1_CORE General purpose interrupt from storage interface 1. Applies only to the FX3Sâ„¢ devices.
14 UNUSED Do not enable.
15 I2C_CORE
General-purpose I2C interrupt; indicates conditions such as
transfer completion, error detect, and so on
16 I2S_CORE General-purpose I2S interrupt
17 SPI_CORE General-purpose SPI interrupt
18 UART_CORE General-purpose UART interrupt
19 GPIO_CORE
General-purpose GPIO interrupt; common for both simple
and complex GPIOs
20 PERIPH_DMA
DMA socket interrupt from any serial peripheral block (I2C,
I2S, SPI, or UART).
21 GCTL_POWER
Power detect interrupt; indicates voltage changes on any
power inputs that can be dynamically changed during
device operation.
This is commonly used for VBus voltage detection.
22-31 UNUSED Do not enable.
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