Cypress EZ-USB CX3 User Manual

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 27
1.10.12 CX3_PHY_TIME_DELAY (Register Address: 0x0060)
This register configures delay parameters for the MIPI CSI-2 Receiver PHY on the CX3 MIPI CSI-2 block. The
settings depend on the CSI_RX_CLK defined in 1.7.3
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
TC TERM
RESERVED
BIT
7
6
5
4
3
2
1
0
NAME
TD TERM
THS SETTLE
Register Field
Bit
Description
TC TERM
[15]
TC TERM Selection:
Set to 1 for normal operation, 0 is not supported.
RESERVED
[14:8]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
TD TERM
[7]
TD TERM selection:
0: Data Lane HS termination occurs after 2 x CSI_Rx_Clk or 3 x CSI_Rx_Clk
time when LP to HS transition.
1: Data Lane HS termination is set immediately when LP to HS transition
(preferred).
THS SETTLE
[6:0]
THS SETTLE Timer:
Timer to control delay between LP to HS transition.
Range: 0x00 - 0x7F.
Delay = (THS SETTLE + 1) x CSI_RX_CLK

Cypress EZ-USB CX3 Specifications

General

Brand	Cypress
Model	EZ-USB CX3
Category	Controller
Language	English