Cypress EZ-USB CX3 - 1.10.10 CX3_CLK_CTRL (Register Address: 0 x0020)

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 25
1.10.10 CX3_CLK_CTRL (Register Address: 0x0020)
This register configures the interface clock dividers for the MIPI CSI-2 block.
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
BIT
7
6
5
4
3
2
1
0
NAME
RESERVED
CSI RX CLK DIV
MCLK REF DIV
PAR OUT CLK DIV
Register Field
Bit
Description
RESERVED
[15:6]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
CSI RX CLK DIV
[5:4]
Clock Divider for CSI RX LP HS Transition Clock:
Divides down from the PLL clock to generate this clock. See Section 1.7.3
for details.
2’b00: PLL CLOCK/8
2’b01: PLL CLOCK/4
2’b10: PLL CLOCK/2
2’b00: RESERVED
This frequency must be between 66-125 MHz.
MCLK REF DIV
[3:2]
Clock Divider for MCLK Reference Clock:
Divides down from the PLL clock to generate the MCLK reference clock. See
Section 1.7.5 for details.
2’b00: PLL CLOCK/8
2’b01: PLL CLOCK/4
2’b10: PLL CLOCK/2
2’b00: RESERVED
This frequency must be less than 125 MHz.
PAR OUT CLK DIV
[1:0]
Clock Divider for Parallel Output Clock (PCLK):
Divides down from the PLL clock to generate the parallel output clock (which
drives the GPIF II interface). See Section 1.7.4 for details.
2’b00: PLL CLOCK/8
2’b01: PLL CLOCK/4
2’b10: PLL CLOCK/2
2’b00: RESERVED
This frequency cannot be greater than 100 MHz.