Cypress EZ-USB CX3 - 1.10.3 CX3_FIFO_CTRL (Register Address: 0 x0006)

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 18
1.10.3 CX3_FIFO_CTRL (Register Address: 0x0006)
This register determines the FIFO trigger level for the initiation of parallel data output from the parallel output
buffer of the MIPI CSI-2 block. The MIPI CSI-2 block waits for the parallel output buffer to reach the level
specified by this register before transferring data to GPIF II interface.
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
RESERVED
FIFO LEVEL[8]
BIT
7
6
5
4
3
2
1
0
NAME
FIFO LEVEL [7:0]
Register Field
Bit
Description
RESERVED
[15:9]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
FIFO LEVEL
[8:0]
FIFO Level:
Determines the FIFO Write trigger level. The MIPI CSI-2 block starts parallel
output to the GPIF II only when the output buffer reaches this level.
Range: 0x000-0x1FF