Cypress EZ-USB CX3 User Manual

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 20
1.10.5 CX3_MCLK_CTRL (Register Address: 0x000C)
This register configures the MCLK divider and controls the Image Sensor Reference Clock (MCLK) output
from the MIPI CSI-2 block. Detailed information on calculating the MCLK value is provided in Section 1.7.5 .
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
MCLK HIGH
BIT
7
6
5
4
3
2
1
0
NAME
MCLK LOW
Register field
Bit
Description
MCLK HIGH
[15:8]
MCLK HIGH Time Count:
HIGH time count for the MCLK divider. See Section 1.7.5 for details on this
field.
MCLK is enabled only if MCLK HIGH and MCLK LOW are non-zero.
MCLK LOW
[7:0]
MCLK LOW Time Count:
LOW Time count for MCLK divider. See Section 1.7.5 for details on this
field.
MCLK Divider = (MCLK HIGH +1) + (MCLK LOW+1)

Cypress EZ-USB CX3 Specifications

General

Brand	Cypress
Model	EZ-USB CX3
Category	Controller
Language	English