Cypress EZ-USB CX3 - 1.10.8 CX3_PLL_CTRL0 (Register Address: 0 x0016)

Cypress EZ-USB CX3
EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 23
1.10.8 CX3_PLL_CTRL0 (Register Address: 0x0016)
This register configures the PLL clock on the MIPI CSI-2 block. Detailed description of how the PLL Clock is
generated based on the values from CX3_PLL_CTRL0 (Register Address: 0x0016) and CX3_PLL_CTRL1
(Register Address: 0x0018) is provided in Section 1.7.2
This register is set by the CyU3PMipicsiSetIntfParams() API and queried using the
CyU3PMipicsiQueryIntfParams() API.
BIT
15
14
13
12
11
10
9
8
NAME
PLL PRD
RESERVED
PLL FBD [8]
BIT
7
6
5
4
3
2
1
0
NAME
PLL FBD [7:0]
Register Field
Bit
Description
PLL PRD
[15:12]
Input Divider:
Input divider for PLL generation. See Section 1.7.2 for details on this field.
Range: 0x0 - 0xF.
RESERVED
[11:9]
RESERVED. Firmware must preserve their settings by reading them,
changing non-reserved bits, and re-writing them.
PLL FBD
[8:0]
Feedback Divider:
Feedback divider for PLL generation. See Section 1.7.2 for details on this
field.
Range: 0x000 - 0x1FF.