3.2 Serial interfaces
• In addition to the USB and peripheral interfaces, FX2LP contains:
• An I
2
C master (only) which operates at 100 or 400 kHz.
• Two standard 8051 USARTs. These are standard UARTs with a synchronous option. The USART interface pins
are available on separate I/O pins, not multiplexed with GPIO pins.
• Up to 40 GPIOs. These pins are multi-purpose, serving as GPIO pins or pins that support the Slave FIFO or
GPIF interfaces. The Package Choices section illustrates these interface options.
3.3 CPU and Memory
3.3.1 8051
• FX2LP has an 8051 core with two USARTs, three counter/timers, and an enhanced interrupt system. The core
can use a 48 MHz, 24 MHz, or 12 MHz clock. The CPU is supported by 16KB of on-chip code/data RAM.
• The enhanced interrupt system uses an “Autovector” mechanism to automatically call one of the 27 USB
interrupt service routines (ISRs), depending on the USB activity that requires service. Automatically
incrementing pointer hardware (“Autopointers”) speed up block transfers.
3.3.2 Boot Options
• FX2LP uses RAM for program storage. FX2LP has the following boot options:
USB boot.
I
2
C boot.
Boot from external parallel memory.
• When connected to USB, its Smart SIE enumerates as a USB bootloader capable of loading program code
into its internal RAM. After the code is loaded, FX2LP electrically disconnects itself from USB and
immediately reconnects as the device defined by the downloaded code. This process is called
Re-Numeration™.
• The FX2LP program RAM also can be loaded at power-on from an external serial EEPROM. Boot options are
detailed in AN50963 - EZ-USB® FX1™/FX2LP™ Boot Options.
3.3.2.1 Package Choices
FX2LP is available in three packages, as Figure 5 shows:
• 56-pin SSOP, QFN, and VFBGA.
• 100-pin TQFP package.
• 128-pin TQFP package.
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