Figure 5 Three FX2LP Package Choices
The 56-pin package is the lowest-cost version of FX2LP. The signals on the left edge of the 56-pin block (in
Figure 5) are common to all package versions in the family. Three modes are available in all package versions:
single-chip, GPIF, and Slave FIFO. These modes define the signals shown on the right edge of the 56-pin block
(in Figure 5). The 8051 selects the interface mode using an internal register. Single-chip mode is the power-on
default configuration.
The 100-pin package adds functionality to the 56-pin package by adding 44 pins:
• Two additional 8-bit I/O ports, PORTC and PORTE.
• Seven additional GPIF controls (CTL) and ready (RDY) signals.
• Nine non-multiplexed control signals (two UARTs, three timer inputs, INT4, and INT5#).
• Eight additional control signals multiplexed on to PORTE.
• Nine GPIF address lines, multiplexed on to PORTC(8) and PORTE(1),
• RD# and WR# signals, which may be used as read and write strobes for PORTC.
The 128-pin package adds 8051 address and data buses and their control signals. These added pins allow
FX2LP to operate with an external 8051 memory. This package is used in the FX2LP Development Board.
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