Cypress EZ-USB FX3 SDK - Page 47

Cypress EZ-USB® FX3™ SDK Quick Start Guide, Version 1.3.1 47
PLL
CSI RX LP <->HS CLK DIVIDER
(2/4/8)
PARALLEL OUTPUT CLOCK (PCLK)
DIVIDER
(2/4/8)
MCLK
DIVIDER
(2/4/8)
MCLKCTL DIVIDER
(MCLK_LOW + MCLK_HIGH)
PLL_CLKREFCLK
CSI_RX_CLK
PCLK
MCLK
Figure 7-2: CX3 MIPI CSI-2 Interface Clocks
A brief description of each of the clocks is provided below:
1. Reference Clock (REFCLK)
This is the input reference clock provide to the MIPI-CSI interface. This input clock
should be between 6 and 40 MHz.
2. PLL Clock (PLL_CLK)
The PLL_CLK is the primary clock on the MIPI CSI-2 interface. The minimum legal
value for PLL clock is 62.5 MHz and maximum legal value for the PLL is 1 GHz.
All other internal/output clocks are derived from this clock.
The PLL clock frequency is generated from the Input Reference Clock using the
following equation:
PLL_CLK = REFCLK * [(pllFbd + 1)/(pllPrd + 1) ] /(2^pllFRS)
where
pllPrd is the input divider whose range is between 0 and 0x0F.
pllFbd is the feedback divider whose range is between 0 and 0x1FF.
pllFRS is the frequency range selection parameter which takes the following
values:
0 if PLL Clock is between 500MHz- 1GHz.
1 if PLL Clock is between 250MHz- 500MHz.
2 if PLL Clock is between 125MHz- 250MHz.
3 if PLL Clock is between 62.5MHz- 125MHz.
E.g.: