Cypress EZ-USB FX3 SDK - Page 48

Cypress EZ-USB® FX3™ SDK Quick Start Guide, Version 1.3.1 48
If RefClk is 19.2 MHz, pllFbd is 69, pllPrd is 1, and PLL Clock range is in the
500MHz-1GHz range (i.e. pllFrs = 0),
PLL_Clock (MHz) = 19.2 * [(69+1)/(1+1)]/(2^0)
= 19.2 * [70/2]/1
= 672 MHz
For the same values, changing PLL frequency range to 125-250MHz (pllFrs = 2)
will change the PLL Clock value to
PLL_Clock (MHz) = 19.2 * [(69+1)/(1+1)]/(2^2)
= 19.2 * [70/2]/4
= 168 MHz
3. CSI RX LPHS Transition Clock
This clock is used for detecting the CSI link LP<->HS transition. It is generated by
dividing the PLL_Clock by a value of 2, 4 or 8.
The minimum value for this clock is 10Mhz and maximum value for this clock is
125MHz.
4. Output Parallel Clock (PCLK)
This clock is the PCLK output which drives the fixed-function GPIF interface on the
CX3. It is generated by dividing the PLL_Clock by a value of 2, 4 or 8.
The maximum value for this clock is 100MHz.
5. MCLK
The MCLK is an optional clock output which can be used as the input reference
clock for the image sensor. It is sourced from the PLL_Clk by first dividing down
using the mClkRefDiv (2/4/8) and then dividing using the MCLKCTL divider. The
MCLKCTL divider specifies the high time and low time counted by the divided down
PLL_CLK.
The upper 8 bits define the high time count (1-255) and the lower 8 bits define the
low time count (1-255).
MCLK is computed using the following equation:
MCLK = (PLL_CLK/mClkRefDiv)/[(HighByte(mClkCtl)+1)+(LowByte(mclkCtl)+1)]
Eg:
If PLL_CLOCK is 672 MHz as given above, to generate MCLK of 24 MHz, we set
mClkRefDiv to 4, mClkCtl to 0x0203 to get
MCLK = (672/4) / ((2+1) + (3+1))
= 168/ 7 = 24 MHz
The MCLK is only output when both HighByte(mClkCtl) and LowByte(mClkCtl) are
non-zero.