Denon AVR-4810CI - Page 24

24
AVR-4810CI/AVR-4810
12
There was invalid data in the firm-
ware for rewriting sent from
DM870 to Main CPU (when a
Check Sum error).
Turn the power off then back on.
Updating starts automatically.
13
The deletion of block data failed
before rewriting Main CPU.
Turn the power off then back on.
Updating starts automatically.
14
The rewriting of block data failed
when rewriting Main CPU.
Turn the power off then back on.
Updating starts automatically.
15
The data verification was invalid
after rewriting Main CPU.
Turn the power off then back on.
Updating starts automatically.
36
Log-in to DPMS has failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Carry out the update in an environment
that has little network load.
37
Line, etc., is busy when logging
into DPMS when rewriting firm-
ware such as Sub CPU, DSP,
FPGA, and PLD.
Carry out the update in an environment
that has little network load.
38
Connection to DPMS failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
39
Connection to DPMS timed out
when rewriting firmware such as
Sub CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
3A
Error (NG) message received
when downloading firmware when
rewriting Main CPU.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
3B
Error (line congestion) message
received when downloading firm-
ware when rewriting Main CPU.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
3C
Error (connection failure) mes-
sage received when downloading
firmware when rewriting Main
CPU.
Turn the power off then back on.
Updating starts automatically.
Carry out the update in an environment
that has little network load.
50
Log-in to DPMS has failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Carry out the update in an environment
that has little network load.
51
Line, etc., is busy when logging
into DPMS when rewriting firm-
ware such as Sub CPU, DSP,
FPGA, and PLD.
Carry out the update in an environment
that has little network load.
52
Connection to DPMS failed when
rewriting firmware such as Sub
CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
53
Connection to DPMS timed out
when rewriting firmware such as
Sub CPU, DSP, FPGA, and PLD.
Check the network connection.
Carry out the update in an environment
that has little network load.
Error
code
Details of Error code Display Coping strategies
M
ain
***
mi n
U
pda t i ng f a i l 12
M
ain
***
mi n
E
rase fai l 13
M
ain
***
mi n
U
pda t i ng f a i l 14
M
ain
***
mi n
U
pda t eCheckNG 15
L
og i n f a i l ed
36
S
erver is busy
37
C
onnec t i on f a i l
38
C
onnec t i on f a i l
39
D
own l o ad f a i l
3A
D
own l o ad f a i l
3B
D
own l o ad f a i l
3C
S
ub
***
mi n
L
og i n fa i l ed 50
S
ub
***
mi n
S
erver is busy51
S
ub
***
mi n
C
onnec t i onFa i l 52
S
ub
***
mi n
C
onnec t i onFa i l 53