ADV7623 Block diagram
CH0
CH1
CH2
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
XTAL
XTAL1
RXA_C
RXB_C
RXC_C
RXD_C
RXA_0
RXA_1
RXA_2
VIDEO/AUDIO
CLOCK
GENERATION
RX
PLL
CEC
TXC
TX0
TX1
TX2
5V DETECT
COMPONENT
PROCESSOR
SCL
SDATA
ALSB
CS
I
2
C
CONTROLLER
PWRDN
RESET
GLOBAL
CONTROLS
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
AP0_IN
AP1_IN
AP2_IN
AP3_IN
AP4_IN
AP5_IN
SCLK_IN
MCLK_IN
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
AP5_OUT
SCLK_OUT
MCLK_OUT
ARC+
RX EDID/
REPEATER
CONTROLLER
RX HPD
CONTROLLER
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SPI MASTER/
SLAVE
EQUALIZER
RXB_0
RXB_1
RXB_2
EQUALIZER
SAMPLER
SAMPLER
RXC_0
RXC_1
RXC_2
EQUALIZER
SAMPLER
RXD_0
RXD_1
RXD_2
EQUALIZER
CEC
CONTROLLER
EDID
RAM
SAMPLER
HDMI RECEIVER
PROCESSOR
TRANSMITTER
PACKET BUILDER
HDCP
ENCRYPTION
ENGINE
HDMI
ENCODER
SERIALIZER
TMDS DRIVERS
INT1
INT2
INT_TX
INTERRUPT
CONTROLLER
TXDDC_SDA
TXDDC_SCL
TX
EDID/HDCP
CONTROLLER
EDID/HDCP
BUFFER
HPD_ARC–
TX HPD
CONTROLLER
HDCP
DECRYPTION
ENGINE
SYNC
MEASUREMENT
PACKET
PROCESSOR
INFOFRAME
PACKET
MEMORY
AUDIO
PROCESSOR
ARC
RECEIVER
AUDIO
CAPTURE
HDCP KEYS
TX
PLL
ADV7623
5V_DETA
5V_DETB
5V_DETC
5V_DETD
HP_CTRLA
HP_CTRLB
HP_CTRLC
HP_CTRLD
OSD
DIGITAL_HDMI_ADV7623 : IC732
MX25L3206EM2I-12G (except : E2)
MX25L6406EM2I-12G (ONLY E2)
SN74CBT3251PWR (DIGITAL_HDMI_ADV7623 : IC733)
Block diagram
CS#
1
2
3
4
8
7
6
5
SO/SIO1
WP#
GND
VCC
HOLD#
SCLK
SI/SIO0
SYMBOL
CS#
SI/SIO0
SO/SIO1
SCLK
WP#
HOLD#
VCC
GND
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O)/ Serial Data
Output (for Dual Output mode)
Clock Input
Write protection
+ 3.3V Power Supply
Ground
Hold, to pause the device without
deselecting the device
DESCRIPTION
PIN DESCRIPTION
SN74CBT3251
1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER
SCDS019L − MAY 1995 − REVISED JANUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B4
B3
B2
B1
A
NC
OE
GND
V
CC
B5
B6
B7
B8
S0
S1
S2
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
RGY PACKAGE
(TOP VIEW)
1 16
89
2
3
4
5
6
7
15
14
13
12
11
10
B5
B6
B7
B8
S0
S1
B3
B2
B1
A
NC
OE
B4
S2
V
GND
CC
NC − No internal connection
description/ordering information
The SN74CBT3251 is a 1-of-8 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-state
resistance of the switch allows connections to be made with minimal propagation delay.
When output enable (OE
) is low, the SN74CBT3251 is enabled. S0, S1, and S2 select one of the B outputs for
the A-input data.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBT3251RGYR CU251
SOIC − D
Tape and reel SN74CBT3251DR
CBT3251
−40°C to 85°C
SSOP − DB Tape and reel SN74CBT3251DBR CU251
SSOP (QSOP) − DBQ Tape and reel SN74CBT3251DBQR CU251
TSSOP − PW
Tape and reel SN74CBT3251PWR
CU251
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBT3251
1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER
SCDS019L − MAY 1995 − REVISED JANUARY 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
OE S2 S1 S0
FUNCTION
L L L L A port = B1 port
L L L H A port = B2 port
L L H L A port = B3 port
L L H H A port = B4 port
L H L L A port = B5 port
L H L H A port = B6 port
L H H L A port = B7 port
L H H H A port = B8 port
H X X X Disconnect
logic diagram (positive logic)
B5
B1
A
B2
B3
B4
B6
B7
B8
OE
S0
S1
S2
5
7
11
10
9
4
3
2
1
15
14
13
12
41
Caution in
servicing
Electrical Mechanical Repair Information Updating
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