Denon DN-HD2500 - Page 29

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DN-HD2500
106 MEAS O B6TS measurement mode setting signal (PANEL 1, 2 is common)
107 SETUP O N B6TS operating mode change signal (PANEL 1, 2 is common)
108 OCHG_2 I PANEL 2: B6TS input 0 / CHG signal output
109 VCCIO3 VCCIO3
110 1SCS_2 IO PANEL 2: B6TS input 1 / CS signal output
111 GND GND
112 2SCK_2 IO PANEL 2: B6TS input 2 / SCK signal output
113 3SD_2 IO PANEL 2: B6TS input 3 / DATA signal output
114 PNL_SCK O PANEL clock
115 P_LEDDAT O PANEL LED data output
116 PNL_KEYDAT I PANEL SW & ENC signal output
117 OCHG1 I PANEL 1: B6TS input 0 / CHG signal output
118 1SCS1 IO PANEL 1: B6TS input 1 / CS signal output
119 2SCK1 IO PANEL 1: B6TS input 2 / SCK signal output
120 3SD1 IO PANEL 1: B6TS input 3 / DATA signal output
121 nSTATUS nSTATUS Configuration I/O (CPU:PE3)
122 VCCIO3 VCCIO3
123 CONF_DONE CONF_DONE (CPU:PE4)
124 GND GND
125 MSEL1 MSEL1 GND
126 MSEL0 MSEL0 3.3V
127 TI710_HHWIL O (ADSP:UHPI_HHWIL:H1:Half-word 1st:0 / 2nd:1)
128 TI710_RST O N DA710 reset signal output
129 PNL_CUE2 I N Fader start signal
130 PNL_PLAY2 I N Fader start signal
131 PNL_CUE1 I N Fader start signal
132 PNL_PLAY1 I N Fader start signal
133 TI710_HBE O N (Audio DSP:UHPI_HBE0:C6, UHPI_HBE1:C5)
134 TI710_HRDY I N Host ready signal (Audio DSP:/UHPI_HRDY:D6)
135 TIDSP_HRD O N (ADSP:UHPI_HDS1:D7)
136 VCCIO3 VCCIO3
137 TIDSP_HWE O N (ADSP:UHPI_HDS2:C7)
138 TI710_HCS O N ADSP chip select (Audio DSP:UHPI_HCS:C8)
139 TIDSP_HR_W O (ADSP:UHPI_HRW:D8)
140 GND GND
141 TIDSP_HCNTL0 O (ADSP:UHPI_HBE0:D9, VDSP:HCNTL0:R3)
142 TIDSP_HCNTL1 O (ADSP:UHPI_HCNTL1:C10)
143 TI710_HIRQ I N ADSP interrupt (Audio DSP:AMUTE2)
144 ISP1761_RST O Not used
145 SH_WE I N Data write enable (CPU:DQMLL)
146 SH_AD13 I 14 bits address 1 (CPU)
147 SH_AD12 I 14 bits address 1 (CPU)
148 VCCIO3 VCCIO3
149 SH_AD11 I 14 bits address 1 (CPU)
150 SH_AD10 I 14 bits address 1 (CPU)
151 SH_AD9 I 14 bits address 1 (CPU)
152 SH_AD8 I 14 bits address 1 (CPU)
153 GND GND
154 GND_PLL2 GND_PLL2
155 VCCD_PLL2 VCCD_PLL2
156 GND_PLL2 GND_PLL2
157 VCCA_PLL2 VCCA_PLL2
158 GNDA_PLL2 GNDA_PLL2
159 GND GND
160 SH_AD7 I 14 bits address 1 (CPU)
161 SH_AD6 I 14 bits address 1 (CPU)
162 SH_AD5 I 14 bits address 1 (CPU)
163 SH_AD4 I 14 bits address 1 (CPU)
164 SH_AD3 I 14 bits address 1 (CPU)
165 SH_AD2 I 14 bits address 1 (CPU)
166 VCCIO2 VCCIO2
167 GND GND
168 SH_AD1 I 14 bits address 1 (CPU)
169 SH_RW I Data R/W (CPU:RD/-WR)
170 SH_DB12 IO 32 bits data bus (CPU)
171 SH_DB13 IO 32 bits data bus (CPU)
172 VCCIO2 VCCIO2
Pin No Pin name I/O Pol Function