Denon DN-HD2500 - Page 36

36
DN-HD2500
ISP1761BE (IC403)
Block Diagram
XTAL1
XTAL2
11
12
CLKIN
13
BUS INTERFACE:
MEMORY
MANAGEMENT
UNIT
+
SLAVE DMA
CONTROLLER
+
INTERRUPT
CONTROL
HC PTD
MEMORY
(3 kB)
MEMORY ARBITER
AND FIFO
TRANSACTION
TRANSLATOR
(TT) AND RAM
OTG CONTROLLER
004aaa450
PLL
30 MHz
60 MHz
GLOBAL CONTROL
AND POWER
MANAGEMENT
DIGITAL
AND ANALOG
OVERCURRENT
PROTECTION
D[15:0]/D[31:0]
GENERIC PROCESSOR BUS
SEL16/32
REGISTERS
SUPPORT
DC BUFFER
MEMORY
8 KBYTES
ADVANCED
PHILIPS
SLAVE HOST
CONTROLLER
ADVANCED
PERIPHERAL
CONTROLLER
DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC
ID
37 to 39, 41 to 43,
45 to 47, 49, 51,
52, 54, 56 to 58,
60 to 62, 64 to 66,
68 to 70, 72 to 74,
76 to 78, 80
82, 84, 86, 87,
89, 91 to 93,
95 to 98,
100 to 103, 105
106
CS_N
107
RD_N
108
WR_N
112
HC_IRQ
113
DC_DREQ
111
DC_IRQ
V
CC(I/O)
10, 40, 48, 59, 67,
75, 83, 94, 104, 115
ISP1761BE
RESET_N
HC_SUSPEND/
WAKEUP_N
122
119
DC_SUSPEND/
WAKEUP_N
120
GNDD
14, 36, 44, 55, 63,
71, 79, 90, 99, 109
POWER-ON
RESET AND
V
BAT
ON
5 V-TO-1.8 V
VOLTAGE
REGULATOR
V
CC(5V0)
BAT_ON_N
5 V-TO-3.3 V
VOLTAGE
REGULATOR
REG3V3
REG1V8
9
6, 7
110
5, 50,
85, 118
REF5V
2
HI-SPEED
USB ATX1
DP1
DM1
PSW1_N
OC1_N/
V
BUS
PSW2_N
OC2_N
PSW3_N
OC3_N
HI-SPEED
USB ATX2
HI-SPEED
USB ATX3
DP2
DM2
DP3
DM3
20
18
27
25
21
127
19
GNDA
26
GNDA
28
128
34
32
33
GNDA
35
1
RREF1
16
GND
(RREF1)
15
RREF2
23
GND
(RREF2)
22
RREF3
30
GND
(RREF3)
29
3
116
HC_DACK
117
DC_DACK
114
HC_DREQ
CHARGE
PUMP
124
C_B
C_A
125
126
V
CC(C_IN)
A[17:1]
17
HC PAYLOAD
MEMORY
(60 kB)
4, 17, 24,
31, 123
GNDA
8
GND(OSC)
53, 88, 121
GNDC
102
103
65
64
38
39
1
128
pin 1 index