Denon DRA-100

CSRA6601(IC1701)
2 Packaging Information
2.1 CSRA6601 Pinout Diagram
G-TW-0011588.1.2
C2P1V8 CH2_REF0 C2P3V3 C2GND CH2_REF1 CH2_REF2 CH2_FB0 CH2_FB1 C23P3V3 C23GND C23P1V8
CH3_FB1 CH3_FB0 CH3_REF2 CH3_REF1 C3GND C3P3V3 CH3_REF0
C3P1V8 CKIGND2 MCK_IN_BAR CKIP3V3 MCK_IN
CKIGND1 CKIP1V8 C4P1V8 CH4_REF0 C4P3V3 C4GND CH4_REF1 CH4_REF2 CH4_FB0 CH4_FB1 C45P3V3 C45GND C45P1V8 CH5_FB1 CH5_FB0 CH5_REF2 CH5_REF1 C5GND C5P3V3 CH5_REF0 C5P1V8
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148
147 146 145 144 143 142 141 140 139 138 137
136
135 134 133
MCK0_OUT 1 132 MCK1_OUT
MCK0_OUT_BAR 2 131 MCK1_OUT_BAR
CKO0P1V8 3 130 CKO1P1V8
CKO0GND 4 129 CKO1GND
PWMCK0_OUT 5 128 PWMCK1_OUT
CKO0P3V3 6 127 CKO1P3V3
P1V8 7 126 P1V8
GND 8 125 GND
C1P1V8 9 124 C6P1V8
CH1_REF0 10 123 CH6_REF0
C1P3V3 11 122 C6P3V3
C1GND 12 121 C6GND
CH1_REF1 13 120 CH6_REF1
CH1_REF2 14 119 CH6_REF2
CH1_FB0 1 5 118 CH6_FB0
CH1_FB1 1 6 117 CH6_FB1
C01P1V8 17 116 C67P3V3
C01GND 18 115 C67GND
C01P3V3 19 114 C67P1V8
CH0_FB1 2 0 113 CH7_FB1
CH0_FB0 2 1 112 CH7_FB0
CH0_REF2 22 111 CH7_REF2
CH0_REF1 23 110 CH7_REF1
C0GND 24 109 C7GND
C0P3V3 25 108 C7P3V3
CH0_REF0 26 107 CH7_REF0
C0P1V8 27 106 C7P1V8
P1V8 28 105 P1V8
GND 29 104 GND
P3V3 30 103 P3V3
CH3_PWM2 31 102 CH4_PW M2
CH3_PWM1 32 101 CH4_PWM1
CH3_PWM0 33 100 CH4_PWM0
CH2_PWM2 34 99 CH5_PWM2
CH2_PWM1 35 98 CH5_PWM1
CH2_PWM0 36 97 CH5_PWM0
GND 37 96 GND
P3V3 38 95 P3V3
CH1_PWM2 39 94 CH6_PWM2
CH1_PWM1 40 93 CH6_PWM1
CH1_PWM0 41 92 CH6_PWM0
CH0_PWM2 42 91 CH7_PWM2
CH0_PWM1 43 90 CH7_PWM1
CH0_PWM0 44 89 CH7_PWM0
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
P3V3
GND
P1V8
CH_0_1_AUDIO_SCK
CH_0_1_AUDIO_SD
CH_0_1_AUDIO_WS
CH_2_3_AUDIO_SCK
CH_2_3_AUDIO_SD
CH_2_3_AUDIO_WS
PWM_MODE
GPIO_0 GPIO_1
P3V3
GND
P1V8
GPIO_2
INTERRUPT
BRIDGE_ON
RESET_BAR
MCK_SEL
GPIO_3
GND
P3V3
GPIO_4 GPIO_5
TEST
SPI_CK SPI_CS
SPI_DATA
P1V8
GND
P3V3
GPIO_6 GPIO_7
VPD
CH_4_5_AUDIO_WS
CH_4_5_AUDIO_SD
CH_4_5_AUDIO_SCK
CH_6_7_AUDIO_WS
CH_6_7_AUDIO_SD
CH_6_7_AUDIO_SCK
P1V8
GND
P3V3
Figure 2.1: CSRA6601 Pinout Diagram
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Page 14 of 181
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CSRA6600/CSRA6601 Direct Digital Feedback Amplifier
Data Sheet
2.2 CSRA6601 Device Terminal Functions
Pin Name Function Description
1 MCK0_OUT Output, tristate 108 MHz Master clock output channels 0,
1, 2, 3
2 MCK0_OUT_BAR Output, tristate 108 MHz Master clock bar output
channels 0, 1, 2, 3
3 CKO0P1V8 - 1.8 V core supply (quiet)
4 CKO0GND - Ground
5 PWMCK0_OUT Output, tristate PWM triangle generator output channels
0, 1, 2, 3
6 CKO0P3V3 - 3.3 V I/O supply (quiet)
7 P1V8 - 1.8 V core supply (quiet)
8 GND - Ground
9 C1P1V8 - 1.8 V core supply (quiet)
10 CH1_REF0 Output, tristate Channel 1 reference 0 output
11 C1P3V3 - 3.3 V I/O supply (quiet)
12 C1GND - Ground
13 CH1_REF1 Output, tristate Channel 1 reference 1 output
14 CH1_REF2 Output, tristate Channel 1 reference 2 output
15 CH1_FB0 Bidirectional, pull-up Channel 1 low resolution feedback input
or channel 0/1 I²S output word clock
16 CH1_FB1 Bidirectional, pull-up Channel 1 high resolution feedback input
or channel 0/1 I²S output data
17 C01P1V8 - 1.8 V core supply (quiet)
18 C01GND - Ground
19 C01P3V3 - 3.3 V I/O supply (quiet)
20 CH0_FB1 Bidirectional, pull-up Channel 0 high resolution feedback input
or channel 0/1 I²S output bit clock
21 CH0_FB0 Bidirectional, pull-up Channel 0 low resolution feedback input
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Page 15 of 181
CS-225959-DSP6
www.csr.com
CSRA6600/CSRA6601 Direct Digital Feedback Amplifier
Data Sheet
69