www.dfi .comChapter 3 Hardware Installation
20
Chapter 3
USB_SSRX2+ C10 USB Port 2, SuperSpeed RX +
USB_SSRX2- C9 USB Port 2, SuperSpeed RX -
USB_SSTX3+ D13 AC Coupling capacitor USB Port 3, SuperSpeed TX +
USB_SSTX3- D12 AC Coupling capacitor USB Port 3, SuperSpeed TX -
USB_SSRX3+ C13 USB Port 3, SuperSpeed RX +
USB_SSRX3- C12 USB Port 3, SuperSpeed RX -
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
LVDS_A0+/eDP_TX2+ A71
LVDS_A0-/eDP_TX2- A72
LVDS_A1+/eDP_TX1+ A73
LVDS_A1-/eDP_TX1- A74
LVDS_A2+/eDP_TX0+ A75
LVDS_A2-/eDP_TX0- A76
LVDS_A3+ A78
LVDS_A3- A79
LVDS_A_CK+/eDP_TX3+ A81
LVDS_A_CK-/eDP_TX3- A82
LVDS_B0+ B71
LVDS_B0- B72
LVDS_B1+ B73
LVDS_B1- B74
LVDS_B2+ B75
LVDS_B2- B76
LVDS_B3+ B77
LVDS_B3- B78
LVDS_B_CK+ B81
LVDS_B_CK- B82
LVDS_VDD_EN/eDP_VDD_EN A77 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K : LVDS panel power enable
LVDS flat panel power enable.
eDP power enable
LVDS_BKLT_EN/eDP_BKLT_EN B79 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K: LVDS panel backlight enable
LVDS flat panel backlight enable high active signal
eDP backlight enable
LVDS_BKLT_CTRL/eDP_BKLT_CTRL B83 O CMOS 3.3V / 3.3V LVDS/eDP: PD 100K: LVDS panel backlight brightness control
LVDS flat panel backlight brightness control
EDP backlight brightness control
LVDS_I2C_CK/eDP_AUX+ A83 I/O OD CMOS 3.3V / 3.3V PU 4.7K: to 3.3V I2C clock output for LVDS display use
DDC I2C clock signal used for flat panel detection and control.
eDP auxiliary lane +
LVDS_I2C_DAT/eDP_AUX- A84 I/O OD CMOS 3.3V / 3.3V PU 4.7K: to 3.3V I2C data line for LVDS display use
DDC I2C data signal used for flat panel detection and control.
eDP auxiliary lane -
RSVD/eDP_HPD A87 I CMOS 3.3V / 3.3V
LVDS: RSV series resistor
to PCH EDP HPD
eDP: Connect to PCH
EDP HPD w
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 0
eDP lane 2, TXƲ
differential signal pair
LVDS Channel A differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-.
LVDS_A_CK+/-, LVDS_B_CK+/-) shall have 100ƻ terminations across the
pairs at the destination. These terminations may be on the Carrier Board if
the Carrier Board implements a LVDS deserializer on-board.
eDP: eDP differential pairs
O LVDS
LVDS channel A differential signal pair 1
eDP lane 1, TXƲ
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 3
LVDS
EDP: AC coupled off
Module
LVDS channel A differential signal pair 2
eDP lane 0, TX Ʋ
differential signal pair
O LVDS
LVDS
EDP: AC coupled off
Module
LVDS channel B differential signal pair 2
LVDS Channel A differential clockO LVDS LVDS
LVDS channel A differential clock pair
eDP lane 3, TXƲ
differential pair
O LVDS
LVDS channel B differential signal pair 0
LVDS channel B differential signal pair 1
LVDS Channel B differential clock
LVDS Channel B differential pairs
Ther LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-.
LVDS_A_CK+/-, LVDS_B_CK+/-) shall have 100ƻ terminations across the
pairs at the destination. These terminations may be on the Carrier Board if
the Carrier Board implements a LVDS deserializer on-board.
O LVDS LVDS LVDS channel B differential signal pair 3
O LVDS LVDS LVDS channel B differential clock pair
AC coupled on Module
Additional transmit signal differential pairs for the SuperSpeed USB data
path.
I PCIE AC coupled off Module
Additional receive signal differential pairs for the SuperSpeed USB data
path.
Signal Pin# Pin Type Pwr Rail /Tolerance CH960 PU/PD Module Base Specification R2.1 Description COM Express Carrier Design Guide R2.0 Description
USB Si
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