faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow
has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in
the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed).
The microcontroller also supports Microsoft Intellimouse-type extensions for reporting back a third axis representing the
mouse wheel, as shown in Table 9.
Command Action
EA Set stream mode. The mouse responds with “acknowledge” (0xFA) then resets its movement counters and
enters stream mode.
F4 Enable data reporting. The mouse responds with “acknowledge” (0xFA) then enables data reporting and
resets its movement counters. This command only affects behavior in stream mode. Once issued, mouse
movement will automatically generate a data packet.
F5 Disable data reporting. The mouse responds with “acknowledge” (0xFA) then disables data reporting and
resets its movement counters.
F3 Set mouse sample rate. The mouse responds with “acknowledge” (0xFA) then reads one more byte from the
host. This byte is then saved as the new sample rate, and a new “acknowledge” packet is issued.
FE Resend. FE directs mouse to re-send last packet.
FF Reset. The mouse responds with “acknowledge” (0xFA) then enters reset mode.
Table 9. Microsoft Intellimouse type extensions, commands, and actions.
When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides physical layer
implementation for any USB 2.0 user-application. It connect to a USB A (J7-bottom row) and a USB AB micro (J6) receptacle
in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors. Use only one of the connectors at a
time, the one fitting the desired USB role.
The transceiver is a TUSB1210 with a UTMI+ low pin interface (ULPI) towards the FPGA. ULPI is a 12-pin SDR interface
clocked at 60
MHz (), resulting in the maximum data rate of 480 Mbps. On the Genesys 2 the transceiver provides the ULPI
clock, which is wired to a clock-capable input pin of the FPGA. Figure 14 shows the connection diagram of the PHY.
The part of the USB 2.0 stack above the physical layer has to be implemented in the FPGA. Xilinx offers an AXI USB 2.0
Device Controller IP that needed separate licensing at the time of writing.
Auxiliary circuitry, like an electronic power switch and jumpers are used to implement different USB roles. In Host
applications, the switch can be commanded through the PHY to power VBUS. The switch has built-in current limit and short
circuit protection. VBUS error conditions are signaled to the FPGA by means of a status pin. In Device role, this switch should
be disabled. A jumper (JP1) in series with the power switch can be used to make sure VBUS is not inadvertently powered.
Another jumper (JP2) (dis)connects a 150 µF capacitor to/from the VBUS. Use it to implement the different bus capacitance
requirements of the USB roles.
12. User USB 2.0
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