Digilent Genesys 2 - Page 33

Signal Name FPGA Pin Pin Function
ADC ()_SDATA AH19 Serialized audio resulting from the analog-to-digital conversion (record).
DAC ()_SDATA AJ19 Serialized audio is converted to analog by the codec (playback).
BCLK AG18 Serial data port clock.
LRCLK AJ18 Serial data port frame clock.
MCLK AK19 Master clock.
SDA AF18 I2C configuration interface.
SCL AE19 I2C configuration interface.
Table 19. Audio signal description.
reference (https://reference.digilentinc.com/tag/reference?do=showtag&tag=reference), programmable-logic
(https://reference.digilentinc.com/tag/programmable-logic?do=showtag&tag=programmable-logic), genesys-2
(https://reference.digilentinc.com/tag/genesys-2?do=showtag&tag=genesys-2), reference-manual (https://reference.digilentinc.com/tag/reference-
manual?do=showtag&tag=reference-manual)
With the exception of CLK3_BIDIR
See the 7-Series FPGAs SelectIO Resources User Guide (
ug471
(http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf)) for details.
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