Chapter 3
H61H2-M17 USER MANUAL
51
Chipset OverClocking Configuration
Scroll to this item to view the following screen:
Main Advanced Chipset M.I.B III Boot Security Exit
The selection of
Performance Memory
Profiles which impacts
memory sizing behavior.
Memory Multiplier Cofiguration
Performance Memory Profiles Automatic
Memory Timing Configuration
CAS# Latency(tCL) 7
RAS# to CAS# Delay(tRCD) 7
Row Precharge Time(tRP) 7
RAS# Active Time(tRAS) 20
Write Recovery Time(tWR) 6
Row Refresh Cycle Time(tRFC) 59
Active to Active Delay(tRRD) 4
Write to Read Delay(tWTR) 4
Read CAS# Precharge(tRTP) 4
Four Active Window Delay(tFAW) 20
+/- : Change Opt.
Enter/Dbl Click : Select
“¤
: Select Screen
/Click: Select Item
F1: General Help
F2: Previous Values
F3: Optimized Defaults
ESC/Right Click: Exit
«‹
F4: Save & Exit
Performance Memory Profiles (Automatic)
This item allows you to select the memory mode: Automatic, Manual, XMP Profile 1
or 2.
CAS# Latency(tCL) (7)
This item determines the operation of DDR SDRAM memory CAS (column address
strobe). It is recommended that you leave this item at the default value. The 2T
setting requires faster memory that specifically supports this mode.
RAS# to CAS# Delay(tRCD) (7)
This item specifies RAS# to CAS# delay to Rd/Wr command to the same bank.
Row Precharge Time(tRP) (7)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
RAS# Active Time(tRAS) (20)
This item specifies the RAS# active time.
Write Recovery Time(tWR) (6)
This item specifies the write recovery time.
Row Refresh Cycle Time(tRFC) (59)
This item specifies the row refresh cycle time.
Active to Active Delay(tRRD) (4)
This item controls the active bank x to active bank y in memory clock cycles.
Write to Read Delay(tWTR) (4)
This item specifies the write to read delay time.
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