Page-9
■ Registers
1. Register table
2. Notes
(1) The counts at addresses 0 to C are all positive logic. Therefore, a register bit that is 1 appears as a high-level signal on
the data bus. Data representation is BCD.
(2) Do not set an impossible date or time in the RTC. If such a value is set, the effect is unpredictable.
(3) When the power is turned on (before the RTC is initialized), the state of all bits is undefined. Therefore, write to all
registers after power-on, to set initial values. For details of the initialization procedure, see "Using the RTC-72421/RTC-
72423" on page 16.
(4) The TEST bit of control register F is used by EPSON for testing. Operation cannot be guaranteed if 1 is written to this bit,
so make sure that it is set to 0 during power-on initialization.
sserddA3A2A1A0AretsigeRataDtnuoCskrameR
)xeH(eman3D2D1D0D)DCB(
0 0000 1S8s4s2s1s9~0retsigertigiddnoces-1
1 0001 01S*04s02s01s5~0retsigertigidsdnoces-01
20010 1IM8im4im2im1im9~0retsigertigidetunim-1
30011 01IM* 04im02im01im5~0retsigertigidsetunim-01
40100 1H8h4h2h1h9~0retsigertigidruoh-1
50101 01H* MA/MP02h01h2ro1~0retsigertigidsruoh-01
60110 1D8d4d2d1d9~0retsigertigidyad-1
7 0111 01D**02d01d3~0retsigertigidsyad-01
8 1000 1OM8om4om2om1om9~0retsigertigidhtnom-1
91001 01OM***01om1~0retsigertigidshtnom-01
A10101Y8y4y2y1y9~0retsigertigidraey-1
B1011 01Y08y04y02y01y9~0retsigertigidsraey-01
C1100W * 4w2w1w6~0retsigerkeew-eht-fo-yaD
D1101DCJDAs-03GALFQRIYSUBDLOHDretsigerlortnoC
E 1110 EC1t0t
/TPRTI
DNTS
KSAMEretsigerlortnoC
F 1111 FCTSET21/42POTSTESERFretsigerlortnoC
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