Espressif Systems ESP32 Series - Adc

2. Schematic Checklist and PCB Layout Design
Notice:
• Please note the requirements for the 32.768 KHz crystal.
– Equivalent series resistance (ESR) ⩽ 70 KΩ.
– Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R4 is used for biasing the crystal circuit (5 MΩ < R4 ⩽ 10 MΩ).
• If the RTC source is not required, then pin12 (32K_XP) and pin13 (32K_XN) can be used as GPIOs.
Figure 7 shows the schematic of the external signal.
32768 kHz signal
ESP32
32K_XN
32K_XP
C1
Figure 7: Schematic of External Oscillator
The value of C1 should be larger than 200 pF. The signal should meet the following requirements:
32K_XN input Amplitude (Vpp, unit: V)
Sine wave or square wave 0.6 < Vpp < VDD
2.1.5 RF
The output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30+j10) Ω and (35+j10) Ω,
respectively. A π-type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network.
CHIP_PU
GPIO35
SENSOR_VP
SENSOR_VN
GPIO34
GPIO32
GND GNDGND
C14
TBD
L4 TBD
C17
270pF(NC)
C15
TBD
C16
270pF(NC)
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
12
ANT1
PCB ANT
1
2
Figure 8: ESP32 RF Matching Schematics
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
2.1.6 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.
• Pins SENSOR_VP or SENSOR_VN will trigger an input glitch lasting for 80 ns once SARADC1, or SARADC2,
or Hall sensor is initialized.
Espressif Systems 7 ESP32 Hardware Design Guidelines V2.7