2. Schematic Checklist and PCB Layout Design
15 mm
Base Board
15 mm
Clearance
15 mm
Figure 13: Keepout Zone for ESP32 Module’s Antenna on the Base Board
2.2.1.3 Power Supply
• Four-layer PCB design
In a four-layer PCB design, the 3.3 V power traces are routed as shown highlighted in yellow in Figure 14.
The width of these power traces should be greater than 25 mil. Before power traces reach the analog power-
supply pins (pin 1, 3, 4, 43, 46), a 10 µF capacitor is required, which can work in conjunction with the 0.1 µF
capacitor. As Figure 14 shows, C13 (10 µF capacitor) is placed by the 3.3 V stamp hole; C10, L5 and C21
are placed as close as possible to the analog power-supply pin. If possible, add a 0.1 µF capacitor for every
digital power pin. Note that all decoupling capacitors should be placed close to the power pin, and ground
vias should be added adjacent to the ground pin for the decoupling capacitors to ensure a short return path.
Figure 14: ESP32 Power Traces in a Four-layer PCB Design
It is good practice to route the power traces on the fourth (bottom) layer. Vias are required for the power
traces to go through the layers and get connected to the pins on the top layer. The diameter of the drill
should exceed the width of the power traces. The diameter of the via pad should be 1.5 times that of the
drill.
Espressif Systems 11 ESP32 Hardware Design Guidelines V2.7
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