Advanced Function Instruction
7-27
FUN 52 D P
SHFR
SHIFT RIGHT
FUN 52 D P
SHFR
D : Register to be shifted
N : Number of bits to be shifted
D, N may combine with V, Z, P0~P9 to serve
indirect address application
WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR
Range
Ope-
rand
WX0
∣
WX240
WY0
∣
WY240
WM0
∣
WM1896
WS0
∣
WS984
T0
∣
T255
C0
∣
C255
R0
∣
R3839
R3840
∣
R3903
R3904
∣
R3967
R3968
∣
R4167
R5000
∣
R8071
D0
∣
D4095
1 1
∣ or ∣
16 32
V、Z
P0~P9
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When shift control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will shift the data of D
register towards the right by N successive bits (in descending order). After the highest bits, B15 or B31 ( D
instruction) have been shifted right, their positions will be replaced by the shift-in bit INB, while shift-out bit
B0 will appear at shift-out bit "OTB".
z If the operand is 16 bit, the effective range of N is 1~16. For 32 bits ( D instruction) operand, it is 1~32.
Beyond this range, will set the N value error flag "ERR" to 1, and do not carry out this instruction.
X0
EN
D :
N :
R 0
OTB
Y0
ERR
INB
52P.SHFR
15
z The instruction at left shifts the data in R0 register
towards the right by 15 successive bits. The
results are shown below.
INB
B15
R0 B0
Y0
0 → 1 0 1 0 101010101010 →
△ *
Ø
X0＝
INB
B15
R0 B0
Y0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0
△ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ *
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