Fluke 8502A - Circuit Analysis Introduction; Detailed Circuit Descriptions; Controller Circuit Analysis; Microprocessor Timing Analysis

8502A
returned at each decision are
accumulated by the Controller
and assembled into
a
24-bit word
describing the polarity
and magnitude of the input.
3-31
, CIRCUIT ANALYSIS
3-32.
Introduction
3-33.
Detailed circuit descriptions
for each module
in
the standard 8502A
mainframe
will be presented
in the
following paragraphs. Optional modules
are covered in
Section 6. Block Diagram Description
should be read
first
to
get an understanding of the
overall functioning
of the
instrument.
Simplified
schematic diagrams are
located in
Section
8
(Section
6 for optional modules).
Table
3-1
is a
list of mnemonic definitions used
in the Controller
schematic.
3-34. Controller
3-35. TIMING
3-36. The 8080
microprocessor requires two
12V clock
inputs
whose phase
relationship must fail
within certain
limits
(Figure 3-9).
The period of
the
<p]
clock
(588
nsec)
governs
the duration
of
a
machine
state
(3
to 5
states
required
for a machine
cycle, 1 to
5 machine
cycles re-
quired for an instruction
cycle). A 1 .7
MHz crystal
oscil-
lator is
RC
coupled through buffers
and gates to
provide
the
two-phase clock signal. R1
controls the positio ning
of the
^1
dock pulse (with
respect
to
time) during the
(j)2
pulse. The
02
clock pulse is inverted and
translated to 5
volt TTL levels for other timing
functions in the control
circuitry.
3-37.
Shaped line pulses are applied to a phase-locked
loop (U26) which runs at 8 times the line frequency
480 Hz for 60 Hz line, 400 Hz
for
50 Hz
line). The output
of U26 is divided
by
8
(U34) and applied
to a
phase
com-
parator (U26). Line
synchronization
is achieved using the
output of the phase-locked loop to time the internal inter-
rupt,
MARK
INT.
3-38.
ADDRESS and DATA BUSSES
3-39. Sixteen address lines
are used for addressing mem-
ory
locations
and external
modules. Refer
to
the
Controller
schematic in Section 8. Internal
scratch pad memory loc-
ations use A0-A7, with
A8,
9,
II,
12,
13 decoded as a RAM
chip
select, internal ROM
locations use AO-AIO, All,
12,
13 decoded as a ROM chip select.
ROM/RAM select uses
A14
for RAM (high for RAM).
External addresses use
A8-A14
with
A15 used as external/internal select (high for
external). These address lines are inverted
when
driving the
IC lines on the Interbus. The data bus is eight lines
(DBO-7)
connected directly to memory and to the externa!
data
bus
(IDO-7)
through tristate I/O buffers.
Table
3-1.
Mnemonic
Definitions
ACK
—
acknowledge
ACK LAT
—
acknowledge late
AR
—
analog return
DB
—
data bus
DBIN
—
data bus
input signal (from qP)
DID ACK
—
delayed ACK
EN INT
—
enable interrupt
HLDA
—
hold acknowledge
IB ADX
—
interbus
address
IBIN
-
interbus input signal
1C
—
interbus control
ID
—
interbus data
lINT
—
internal interrupt
INA
—
interrupt acknowledge
(from
controller)
INT
•—
interrupt
INTA
—
Interrupt acknowledge
(status
word from qP)
INTE
—
interrupt enable
(from qP)
MEM RD
—
memory read
MS ADDR BYTE
—
memory select address
byte
01
—
clock
pulse
02
—
clock
pulse
0LL
—
phase-locked loop
RAM
—
random
access memory
ROM
—
read
only memory
RRDY
—
reset ready
RST
—
reset
RT
—
real time
R/W
—
read/write
mP
—
microprocessor
VA
—
analog supply voltage
Vcc
—
5V
clock
pulse
Vqd
02
—
12V clock
pulse
SRDY
—
set ready
SYN
lINT
—
synchronized
internal
interrupt
TTL PU
—
TTL pull-up
WO
—
write
out
WR
—
write
3-40.
RESET
3-41.
Shaped line frequency pulses are
applied to U36
and U34 to provide
a
reset
on power up or power
down
(Figure 3-10). U36
is a retriggerable one-shot
multivibrator
which
is
cleared
on power up by Delayed Vcc.
Clearing
U36 sets U35 to the Reset
condition. After the clear
on
3-8