8502A
U36 is
removed
(Delayed Vcc high), U34 clocks U35 out of
the reset
condition on the eighth line pulse. At power
down, U36 changes state at
a
time determined
by
R18
and
C22,
setting
U35 to the reset state.
342. STATUS
LATCH
343. During
the first state of every machine cycle, the
microprocessor
sends
a
status word out on the data bus.
This is
at
the
same time and duration
as
the SYNC output.
SYNC
(j>2
clocks the
status word into a hex “D”
latch,
U18. Outputs from U18 (Figure
3-11) are used in various
portions of the control circuitry.
344. WAIT
LOGIC
345. When
the microprocessor addresses
an external
module (A 15 high) or
is
interrupted,
the WAIT logic causes
the microprocessor to enter
a wait state by pulling the
ready (RDY) line low (Figure 3-12).
Set Ready (SRDY).
normally high,
is
pulled low to exit the wait
state. Reset
ready
(RRDY),
normally low, goes high to enter
the wait
state. For an external
address, A15 TTL is high; therefore
RRDY will
go
high
at
SYNC
TTL (derived
from the micro-
processor). For interrupts,
the interrupt enable
(INTE^
signal
is
inverted
for application
to U8.
INTE
enables IN7
and is removed before INT
falls low (due to an RC delay
in the INT CONTROL
circuit) so the INT
and
INTE
are
higli long enough to clock U1
for a wait signal.
346.
Three possible combinations
will cause the micro-
processor to exit a
wait
state. If an ACK
signal
is missing,
ACK INT TTL will pull
SRDY
low.
For external
addresses,
and
externa
l
interrupts,
A1 5
+
INTA and ACK LAX will
puli SRDY low. For internal interrupts SYN
IINT and
Figure 3-10.
Reset Logic
3-9
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