8502A
3-65.
Fast
A/D Converter
3*66. The Fast A/D
Converter may be separated
for
analysis into
two component groups: Analog
and Digital.
Analog
circuitry
is
responsible for producing a
voltage
reference, for summations, and
for remainder
amplification
and storage. Digital circuitry interfaces
the analog circuitry
to the Controller
and is
responsible for reference
selection,
decisions
in
the summation process, remainder
channel
control, and
auto/.eroing. Since functions within
the A/D
Converter are
either directly controlled by the
Controller
module
via the
data
bus or are clocked through
their opera-
tions by
the Controller addressing the A/D
module, the
A/D
conversion program could be considered a
functional
part of the A/D
Converter.
3-67. ANALOG
3-68. Figure
3-18
Is a
simplified schematic of
the analog
portion of the A/D
Converter. For clarity,
switches are
shown as a
circle
enclosing
a letter
designator. U ! is a refer-
ence and
reference amplifier controlling
U2, a
current
source. The
—
7V reference is set by R9 and
R14. U3
serves
as a
highly
regulated collector and /.ener
supply for UI.
Operation of the D/A
Converter requires both a
positive
and
negative reference (for
negative
and
positive inputs,
respectively).
Q9
and
U4 are
a
precision unity gain
ampli-
fier whose input
is
controlled by
switches
A1
and A2. With
A1 open and A2
closed,
Q9
and U4 are configured as an
inverting amplifier producing a
positive reference.
With
A1
closed and A2 open,
Q9
and U4
are
a
noninverting ampli-
fier.
3-69.
An input
signal
is
applied to the summing node of
the remainder
amplifier
(Q27,
U7) through switch i.
Q27
and
U7 are an inverting amplifier with
two
gain
configura-
tions.
During the decision period, switch G is
closed,
apply-
ing
the output of U7
to
polarity detector Q28
and forming
a
feedback
path
through CR5 and CR6. Q28 sends a
polar-
ity
bit
to the digital
portion of the circuitry'. On
tlie
basis of
this first polarity bit, a
reference polarity
is
selected.
3-70. Switches
B, C, D,
E,
and F are closed, one
at a
time, to switch a precise amount of current into the sum-
ming
node.
When
a switch is closed, the opposite
switc^is
opened and
vice versa. For example, when D is
closed, D
is
opened.
After
a
switch
is
closed, a polarity bit is
returned.
If the polarity changed
with respect to the original polarity
selected for a step, the switch is
opened: otherwise it is
left
dosed. The next switch is dosed, a
polarity bit returned
and a decision made, and so on until all
five switches have
been closed (and possibly opened again). This
constitutes
a
decision
period.
3-71. Following the decision period
is the
subtraction
period. Switch G is
opened and switches X and
SX are
dosed to
form
a
feedback path for the remainder
amplifier
through the X channel. A 400K resistor,
R35, sets tire gain
of
Q27 and
U7 at sixteen. The feedback current
compietes
the summation process
and the amplified
remainder is
stored
on CIO in the X channel.
3-72.
For the next decision period
switches SX and X
are opened and switches RX and G arc dosed. Since Q27
and U7
form
an
inverting amplifier, the opposite
polarity
reference (from the
original selection) is automatically
selected. The
amplified remainder
is
applied to the
sum-
ming
node through U6 and R34.
Five
decisions are
made,
followed by a subtraction
period
using
channel Y for feed-
back
and
remainder storage. The first decision-subtraction
period applies the input signal to the summing node.
The
four following steps apply an amplified
remainder, alternat-
ing
between
channel X and channel
Y.
3-73. When a sample is
complete, the
circuits are auto-
zeroed, U8 zeros the remainder
amplifier through
channel
X. Any
offset
is
stored on C!3 at
the noninverting
input of
Q27,
The switching
reference,
Q9
and U4, is
zeroed by first
closing A I and opening
A2 to decrease settling
time. Then
A I
and A2 are both opened and
the Zl and Z2 switches
arc
closed, storing any
offset error on C5.
3-74. DIGITAL
3-75.
For the
following
discussion,
refer
to
the Digital
Fast
A/D
schematic in Section 8. Direct address !C2.
3,
4 latches data into U34 and U35
controlling
input
switch
!,
remainder
channel switches, autozero, and reset (digital).
U31
,
a ring counter, is
clocked
to
the
Cl
state enabling the
indirect address decoder (U33) and
the
polarity
detector
(switch
G).
A polarity
bit is
returned and applied to
U6.
3-76. Indirect address ICl, 2 latches the polarity bit in
U6. enables the tristale transmitter, U5, and clocks U31 to
the C2 state. The
transition of U31 from
Cl to C2 docks
the polarity into Ul
1
(the
uppermost section) whose out-
put determines
whether switch A I or A2 will be dosed
(reference polarity). At
the
same
time, Ul (uppermost
section) is
docked to set the other section of Ul
1
,
dosing
the first
reference switch, B, of the D/A
Converter.
The
next indirect
address clocks
a
new polarity bit (a result of
dosing
the first reference switch B) into U6.
If
the polarity
changed, the
output of U6 will cause a reset of tlte
previous
switdi latch,
opening the previous switch. At termination
of tlic address
the next switch
is
closed. One direct address
and six indirect addresses are
required to complete a step,
The last
indirect address
resets the control logic to the CO
state.
3-16
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