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4.2.1 GPIO
GPIO has the following user-configurable features:
• Configurable output drive strength
• Internal pull-up and pull-down resistors
• Wake-up from high or low level triggers on all pins
• Trigger interrupt on state changes on any pin
• All pins can be used by the PPI task/event system
• One or more GPIO outputs can be controlled through PPI and GPIOTE channels
• All pins can be individually mapped to interface blocks for layout flexibility
• GPIO state changes captured on SENSE signal can be stored by LATCH register
• An event can be generated in each GPIO based on a rising edge, falling edge, or any changing edge.
Current at VSS+0.4 V, output set low, standard drive
Current at VSS+0.4 V, output set low, high drive
Current at VDD-0.4 V, output set high, standard drive
Current at VDD-0.4 V, output set high, high drive
Internal Pull-up Resistance
Internal Pull-down Resistance
4.2.2 Comparator
The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can be
derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on the
operation mode of the comparator.
Main features of the comparator are:
• Input range from 0 V to VDD
• Single-ended mode
• Fully flexible hysteresis using a 64-level reference ladder
• Differential mode
• Configurable 50 mV hysteresis
• Reference inputs (VREF): VDD
• External reference from AIN0 to AIN7 (between 0 V and VDD)
• Internal references 1.2 V, 1.8V and 2.4V
• Three speed/power consumption modes: low-power, normal and high-speed
• Single-pin capacitive sensor support
• Event generation on output changes
• UP event on VIN- > VIN+
• DOWN event on VIN- < VIN+
• CROSS event on VIN+ and VIN- crossing
• READY event on core and internal reference (if used) ready
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