Heathkit H9 - Page 66

SPECIAL CURSOR
MOVEMENTS
Whenever the
logic
array
(IC702)
moves things
around on
the bus in response to a data available
signal, the TPU assumes that a write operation
has
been
performed
and
it
automatically counts the cur-
sor to the
next RAM location.
The two
inputs
to
IC713C monitor the two data avail-
able signals
(DAV,
and DAVn*a) coming
from
the
I/O
circuit
board.
If
either
goes
high,
pin
8
of
IC713C
goes
low. This
causes
the
output
(pin
8) of NAND
gate
IC719C to
go
high. This is the internal
DAV
signal that
is ANDed with
various
TPU cycles
to
generate
0C if
DAV.
1C
if DAV.
and 0B2
if DAV. The 1C if DAV
signal
(from
IC734
pin
6)
drives
one
input
(pin
)
of
IC722B. The other
input
(pin
5)
is
normally hieh
(it
goes
low to
defeat
the count
up)
and the
output
(pin
6)
goes
low
to count up the
+20
RAM
counter.
If
a control character or rubout was
put
on
the bus, the
CC+R output
(from
pin
t8
of the
logic
array) is
latched into flip-flop IC720A. The
Q
output
(pin
2)
of
this flip-flop
disables the cursor
count up
(C.U.
+20)
through IC7OSD and IC729A. In
addition,
if
the spe-
cial character was a carriage return, line feed, or back
space, an additional
signal
is latched into
one of the
flip-flops
of
lC72O
and the appropriate
Q
output is
ANDed with TPU
cycle 1C
(in
IC7a0D, lC721C,
and
lC727D)
to
perform
the appropriate cursor movement.
Ifthe
character is a carriage return, the
+20
counter is
cleared
[S706-7).
If
it was a line feed, the
+72
counter
is
counted up
(S707-2);
or if it was
a
back
space, the
+20
counter is counted
down
(5706-6).
REFRESH INTERRUPT
Normally,
the Terminal handles
data at
a
rate
of one
character
per
vertical retrace
period,
or
sixty
charac-
ters
per
second
(600
BAUD).
IC705A, IC705D,
IC706B,
and IC7188 form
a circuit
that interrupts the
screen refresh
and
starts an
extended TPU
cycle
whenever
data appears
at rates
greater
than 600
BAUD.
One
input
(pin
2)
of
IC705A
is
tied to a logic
0
fthrough
the rear
panel
BAUD rate
switch)
whenever
the BAUD
rate is
greater
than
600. The refresh
inter-
rupt
signal coming
from
the
I/O
circuit
board
(S203-3)
appears
at
pin
3 of IC705A
and it
goes
low whenever
data is
available from
the
UART
or the
parallel
inter-
face. This
causes
a
logic
1. to
appear at the
data input
of
IC706B.
The
next time
that the A",
8", and
C"
inputs
(57O3-7,
-8,
&
-9)
of
IC7188 go
low,
the
output
goes
high.
This
clocks the
logic
1 at the
D
input
through
IC706B
and starts
an
artificial
vertical retrace
period
through
ICTOSD
(pin
13). This stops the
screen
refresh
cycle
and the TPU
can service the incoming data
within
approximately
one-half millisecond. It
stops
the cycle by stopping the
count ups and blanking the
screen.
The
+12
count up is defeated
by forcing an
input
(pin
2) of lC776A
to a
logic
0. The screen
is
blanked by sending
a
logic
0
(Vn')
to the
character
generator
circuit board
(S703-1).
This
artificial
verti-
cal cycle continues until flip-flop IC706B is reset
by
the
"real"
vertical retrace
signal
(Vp)
coming
from
the
character
generator
circuit board
(5703-2)
ANDed
with
TPU cycle T. After the flip-flop is reset,
the
normal TPU
cycle continues under the
control of the
vertical retrace
signal
coming
from the
character
generator
circuit
board.
TRANSMIT PAGE
During
the transmit
page
mode, the
TPU reads a
character from the RAM at
the current cursor
address
and loads it into the
UART and
parallel
output
buf-
fers. In half
duplex, it waits for the transmit buffers to
empty.
In
full duplex, it waits for the buffers to empty
and
it
also waits for the character
to be
echoed
back.
When these conditions
are
satisfied.
the
TPU
counts
the cursor to the next RAM
location. This
process
is
repeated
until the cursor reaches the end of the
page.
When the
last
character
has
been sent, and the cursor
has been counted up to the start of
page position,
the
TPU
senses
that a scroll
possibility
exists, so it turns
off
the transmit
page
mode without
performing
the
scrolling
operation.
The Transmit Page
button
on
the
keyboard
(S704-9)
initiates the
process
by setting flip-flops
IC731C,
lC731D
during TPU cycle
7C. TheQ-output
(pin
B)
signals to logic array IC702 that the transmit
page
mode should begin. On the next TPU 0B2 cycle
(0B2
comes
from
pin
3 of
IC710),
the logic array
loads
data
from
the RAM location addressed by the
cursor
into
the
parallel
and
UART output buffers. Simultane-
ously,
it
sets flip-flop IC7O4A to indicate that a
character has been transmitted. The
Q-
output of
lC704A inhibits
any further character transmissions
until the cursor has
been counted to the next
RAM
location. In half
duplex, the
cursor
is
counted up
automatically during TPU
cycle
1C. In full
duplex,
the character
must be
echoed back from the
external
device and
then counted up. The
automatic count
up
happens
whenever
there is a DAV
signal. For half
duplex,
a
"fake"
DAV
signal
is
generated
byIC725A.
[The
duplex
button drives the
D
input
of
IC725A.)
In
half duplex, a
logic
1
appears
at
the
D input,
while
in