duplex, a logic O appears at the D input. The
load
pulse (0B2.XP'LOAD)
from
pin
15
of
the logic array
clocks the
level
at the D input through flip-flop
lC725A.
The
Q-output
(pin
6)
goes
low
if the duplex
switch is up, which forces
pin
8 of
IC719C
to
go
high
-
indicating
"DAV."
In full
duplex the
fake DAV
does not occur, so the count up has to wait for
the
character
to
be
echoed
back
through the UART.
Flip-flop lC725A is reset
by
pin
16 of the logic array as
a function
of the count up signal and
the
duplex
button. After the flip-flop has been
cleared, another
character will be transmitted
on
the next
0B2
TPU
cycle. When the cursor encounters a carriage return
stored in a RAM location,
the
+20
cursor
count
up is
inhibited
as before, and
the
+20
counter is cleared. At
the
same time, the carriage
return
output
from
special
character latch IC720
(pin
7) is
clocked
into flip-flop
IC73SA by the
0B2.XP.LOAD
pulse.
This is called the
carriage return flip-flop
and the
Q
output
(pin
5)
is
referred
to on the Schematic as
CRFF. On the next
0B2.XP.LOAD cycle the
Q
output addresses
pin
9 of
the logic
array, which
prevents
a
character from being
loaded
from the RAM. Instead,
it
puts
a line feed
character
on
the bus via IC7O7B,IC719A,
lC726A,
IC7268,
and
IC726D,
The A1 and A2
outputs
(57O4-4
and Szo+-e)
of these decoding
gates
turn on the
special character
generator
on the keyboard.
When the TPU
senses that the cursor has reached the
end of a line and it has not
yet
encountered and
transmitted a
carriage
return
and that the auto carry
button is not
pressed,
flip-flop
IC738B
is set and
further
character
loads
from the RAM are inhibited.
lC774B monitors
the FR output
(pin
6)
of
special
character latch IC720 and the EOL.A-doutput
(pin
5)
of RAM IC730.
When both inputs
ofIC71.4B are
high,
pin
6
goes
high.
This means
end of
line.no auto
carry.no carriage
re-
turn. The logic 1 is clocked into
flip-flop IC738B by
the 0B2.XP.LOAD
pulse.
On
the next
0B2
load
cycle,
the
foutput
(pin
S) of this flip-flop causes a carriage
return
to be
put
on the bus by
outputs
A1 and A2.
IC73BA senses
the carriage
return
and is set by the
0B2.XP.LOAD
pulse.
The next
0B2.XP.LOAD
pulse
causes
a
line
feed to be sent. Flip-flop IC738A is reset
by
the output of
NAND
gate
1C721.8. The output of
IC721.B
goes
low for line feed
(from
pin
10 of
lC72O)
and TPU
cycle 1C
(from
pin
4
oflCT28).
As soon as the
flip-flop is
cleared, the character transmission cycle
can start again
for
the new
line.
When the cursor
reaches
the end of
the
page
and
after
it
has been
counted up to
the
start of
page position,
a
scroll
possibility
exists
and a scroll command is
generated.
However, since the
Q
output
(pin
8) of
the
transmit
page
flip-flop
(IC731C
and IC731D) appears
at one
input
(pin
2)
of
IC7a1,A, the
scroll
is inhibited.
The scroll command does, however,
preset
flip-flop
lC725B,
which,
in
turn,
lets
the
next 7C TPU
cycle
reset the transmit
page
flip-flop, terminating the
transmit
page
mode. lC725B is then reset by the next
TPU 0 cycle.
BELL
DETECT
IC716B
and
IC718A
decode the outputs of the
+20
cursor
latch
(P702-7,
-2, -3, -4,
and
-s)
to determine
when the cursor is in
position
number thirteen
(seven
from the end) of the
20
character block. This
information is ANDed in IC716C and IC735C
with
the
end of
line
signal
(from
pin
9 of
IC730), the
data
available keyboard
signal
(S702-6),
and
TPU
cycle
1C.
The
output
(pin
10) of
IC735C
triggers monostable
IC736,
which,
in
turn, enables
pin
1
of speaker driver
lC742A for
approximately 30 milliseconds. The 300
BAUD rate
clock then drives the speaker
throush
lc742A.
The
end of
line
signal
operates
only
from
the
keyboard. IC742B ANDs
the
bell signal from
the
I/O
circuit board
(5703-12)
with TPU
cycle 0B2DAV. It
also
triggers
the
monostable
whenever an ASCII
bell
signal
(or
control G) is detected
during a write
cycle.
POWER
UP
RESET
When the Terminal is first turned
on,
Q701
and
IC7
17 A
generate
a
positive going pulse,
approximately
200 milliseconds
wide, that
is
used
for
a
power
up
reset.
Capacitor
C719
is
totally discharged
before
power
is
turned on. When the S-volt
supply
comes on,
C719
begins to charge through
resistor
R725 and the base
of
Q701.
This turns
Q701
on and
causes
a logic 1 to appear at the
output
(pin
2)
of
lC7'1.7A. As the
charging current decays,
Q701
turns
off and the output of lC7'1.7 A drops back to a
logic
0.
R728 applies
positive
feedback to the base of
Q701
to
speed the transition between logic states. The
positive going pulse
is
used to
initialize
the UART
(UART
XR,
S702-9).IC777D
inverts
the
reset
pulse
and holds the
erase
flip-flop, 1C723,
cleared
for the
duration of the
200
millisecond
pulse.
This
causes a
page
erase.
lC777E
inverts the
pulse
and momentarily
puts
the Terminal in the short form mode. This clears
the
+4
scroll
counter and
puts
character block zero at
the left hand side
of
the
screen.
lC717C
andlC717B
also
invert
the
reset
pulse
and then clear
the
transmit
page
and carriage
return
flip-flops.
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