Hisense MSD6586 - BA2,CSB1,CSB2 Need GND Shielding

5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Close to DDR POWER PIN
DDR3 : MR410=240R/1%
BA2,CSB1,CSB2 need GND shielding
CSB terminator
DDR3#1
DDR3#2
D-CSB1
D-CSB1
D-CSB1
D-CSB2
D-CSB2
D-CSB2
D-DDR3-A0-T1
D-DDR3-A0-T1
D-DDR3-A0-T2
D-DDR3-A0-T2
D-DDR3-A1-T1
D-DDR3-A1-T1
D-DDR3-A1-T2
D-DDR3-A1-T2
D-DDR3-A10-T1
D-DDR3-A10-T1
D-DDR3-A10-T2
D-DDR3-A10-T2
D-DDR3-A11-T1
D-DDR3-A11-T1
D-DDR3-A11-T2
D-DDR3-A11-T2
D-DDR3-A12-T1
D-DDR3-A12-T1
D-DDR3-A12-T2
D-DDR3-A12-T2
D-DDR3-A13-T1
D-DDR3-A13-T1
D-DDR3-A13-T2
D-DDR3-A13-T2
D-DDR3-A14-T1
D-DDR3-A14-T1
D-DDR3-A14-T2
D-DDR3-A14-T2
D-DDR3-A15-T1
D-DDR3-A15-T1
D-DDR3-A15-T2
D-DDR3-A15-T2
D-DDR3-A2-T1
D-DDR3-A2-T1
D-DDR3-A2-T2
D-DDR3-A2-T2
D-DDR3-A3-T1
D-DDR3-A3-T1
D-DDR3-A3-T2
D-DDR3-A3-T2
D-DDR3-A4-T1
D-DDR3-A4-T1
D-DDR3-A4-T2
D-DDR3-A4-T2
D-DDR3-A5-T1
D-DDR3-A5-T1
D-DDR3-A5-T2
D-DDR3-A5-T2
D-DDR3-A6-T1
D-DDR3-A6-T1
D-DDR3-A6-T2
D-DDR3-A6-T2
D-DDR3-A7-T1
D-DDR3-A7-T1
D-DDR3-A7-T2
D-DDR3-A7-T2
D-DDR3-A8-T1
D-DDR3-A8-T1
D-DDR3-A8-T2
D-DDR3-A8-T2
D-DDR3-A9-T1
D-DDR3-A9-T1
D-DDR3-A9-T2
D-DDR3-A9-T2
D-DDR3-BA0-T1
D-DDR3-BA0-T1
D-DDR3-BA0-T2
D-DDR3-BA0-T2
D-DDR3-BA1-T1
D-DDR3-BA1-T1
D-DDR3-BA1-T2
D-DDR3-BA1-T2
D-DDR3-BA2-T1
D-DDR3-BA2-T1
D-DDR3-BA2-T2
D-DDR3-BA2-T2
D-DDR3-CASZ-T1
D-DDR3-CASZ-T1
D-DDR3-CASZ-T2
D-DDR3-CASZ-T2
D-DDR3-CKE-T1
D-DDR3-CKE-T1
D-DDR3-CKE-T1
D-DDR3-CKE-T2
D-DDR3-CKE-T2
D-DDR3-CKE-T2
D-DDR3-DM0
D_DDR3_DM0
D-DDR3-DM0
D-DDR3-DM1
D_DDR3_DM1
D-DDR3-DM1
D-DDR3-DM2
D_DDR3_DM2
D-DDR3-DM2
D-DDR3-DM3
D_DDR3_DM3
D-DDR3-DM3
D-DDR3-DQ0
D_DDR3_DQ0
D-DDR3-DQ0
D-DDR3-DQ1
D_DDR3_DQ1
D-DDR3-DQ1
D-DDR3-DQ10
D_DDR3_DQ10
D-DDR3-DQ10
D-DDR3-DQ11
D_DDR3_DQ11
D-DDR3-DQ11
D-DDR3-DQ12
D_DDR3_DQ12
D-DDR3-DQ12
D-DDR3-DQ13
D_DDR3_DQ13
D-DDR3-DQ13
D-DDR3-DQ14
D_DDR3_DQ14
D-DDR3-DQ14
D-DDR3-DQ15
D_DDR3_DQ15
D-DDR3-DQ15
D-DDR3-DQ16
D_DDR3_DQ16
D-DDR3-DQ16
D-DDR3-DQ17
D_DDR3_DQ17
D-DDR3-DQ17
D-DDR3-DQ18
D_DDR3_DQ18
D-DDR3-DQ18
D-DDR3-DQ19
D_DDR3_DQ19
D-DDR3-DQ19
D-DDR3-DQ2
D_DDR3_DQ2
D-DDR3-DQ2
D-DDR3-DQ20
D_DDR3_DQ20
D-DDR3-DQ20
D-DDR3-DQ21
D_DDR3_DQ21
D-DDR3-DQ21
D-DDR3-DQ22
D_DDR3_DQ22
D-DDR3-DQ22
D-DDR3-DQ23
D_DDR3_DQ23
D-DDR3-DQ23
D-DDR3-DQ24
D_DDR3_DQ24
D-DDR3-DQ24
D-DDR3-DQ25
D_DDR3_DQ25
D-DDR3-DQ25
D-DDR3-DQ26
D_DDR3_DQ26
D-DDR3-DQ26
D-DDR3-DQ27
D_DDR3_DQ27
D-DDR3-DQ27
D-DDR3-DQ28
D_DDR3_DQ28
D-DDR3-DQ28
D-DDR3-DQ29
D_DDR3_DQ29
D-DDR3-DQ29
D-DDR3-DQ3
D_DDR3_DQ3
D-DDR3-DQ3
D-DDR3-DQ30
D_DDR3_DQ30
D-DDR3-DQ30
D-DDR3-DQ31
D_DDR3_DQ31
D-DDR3-DQ31
D-DDR3-DQ4
D_DDR3_DQ4
D-DDR3-DQ4
D-DDR3-DQ5
D_DDR3_DQ5
D-DDR3-DQ5
D-DDR3-DQ6
D_DDR3_DQ6
D-DDR3-DQ6
D-DDR3-DQ7
D_DDR3_DQ7
D-DDR3-DQ7
D-DDR3-DQ8
D_DDR3_DQ8
D-DDR3-DQ8
D-DDR3-DQ9
D_DDR3_DQ9
D-DDR3-DQ9
D-DDR3-DQS0
D_DDR3_DQS0
D-DDR3-DQS0
D-DDR3-DQS0B
D_DDR3_DQS0B
D-DDR3-DQS0B
D-DDR3-DQS1
D_DDR3_DQS1
D-DDR3-DQS1
D-DDR3-DQS1B
D_DDR3_DQS1B
D-DDR3-DQS1B
D-DDR3-DQS2
D_DDR3_DQS2
D-DDR3-DQS2
D-DDR3-DQS2B
D_DDR3_DQS2B
D-DDR3-DQS2B
D-DDR3-DQS3
D_DDR3_DQS3
D-DDR3-DQS3
D-DDR3-DQS3B
D_DDR3_DQS3B
D-DDR3-DQS3B
D-DDR3-ODT-T1
D-DDR3-ODT-T1
D-DDR3-ODT-T2
D-DDR3-ODT-T2
D-DDR3-RASZ-T1
D-DDR3-RASZ-T1
D-DDR3-RASZ-T2
D-DDR3-RASZ-T2
D-DDR3-RESET-T1
D-DDR3-RESET-T1
D-DDR3-RESET-T1
D-DDR3-RESET-T2
D-DDR3-RESET-T2
D-DDR3-RESET-T2
D-DDR3-WEZ-T1
D-DDR3-WEZ-T1
D-DDR3-WEZ-T2
D-DDR3-WEZ-T2
D-DDR3_MCLKD_DDR3-MCLKD_DDR3_MCLK
D-DDR3_MCLK
D_DDR3-MCLK
D-DDR3_MCLKZD_DDR3-MCLKZD_DDR3_MCLKZ
D-DDR3_MCLKZ
D_DDR3-MCLKZ
D-MVREFCA-T1
D-MVREFCA-T1
D-MVREFCA-T2
D-MVREFCA-T2
D-MVREFDQ-T1
D-MVREFDQ-T1
D-MVREFDQ-T2
D-MVREFDQ-T2
D_DDR3_A0D_DDR3_A0
D_DDR3_A1D_DDR3_A1
D_DDR3_A10D_DDR3_A10
D_DDR3_A11D_DDR3_A11
D_DDR3_A12D_DDR3_A12
D_DDR3_A13D_DDR3_A13
D_DDR3_A14 D_DDR3_A14
D_DDR3_A15D_DDR3_A15
D_DDR3_A2D_DDR3_A2
D_DDR3_A3D_DDR3_A3
D_DDR3_A4D_DDR3_A4
D_DDR3_A5D_DDR3_A5
D_DDR3_A6D_DDR3_A6
D_DDR3_A7D_DDR3_A7
D_DDR3_A8D_DDR3_A8
D_DDR3_A9D_DDR3_A9
D_DDR3_BA0D_DDR3_BA0
D_DDR3_BA1D_DDR3_BA1
D_DDR3_BA2D_DDR3_BA2
D_DDR3_CASZD_DDR3_CASZ
D_DDR3_CKED_DDR3_CKE
D_DDR3_CSB1 D_DDR3_CSB2
D_DDR3_ODT D_DDR3_ODT
D_DDR3_RASZ D_DDR3_RASZ
D_DDR3_RESETD_DDR3_RESET
D_DDR3_WEZD_DDR3_WEZ
D_DDR3_A12
D_DDR3_A9
D_DDR3_A5
D_DDR3_A14
D_DDR3_A2
D_DDR3_A10
D_DDR3_A1
D_DDR3_A3
D_DDR3_A11
D_DDR3_A4
D_DDR3_A8
D_DDR3_A13
D_DDR3_A7
D_DDR3_A6
D_DDR3_A0
D_DDR3_A15
D_DDR3_CSB1
D_DDR3_CSB2
D_DDR3_CASZ
D_DDR3_RASZ
D_DDR3_ODT
D_DDR3_WEZ
D_DDR3_RESET
D_DDR3_MCLKZ
D_DDR3_MCLK
D_DDR3_CKE
D_DDR3_BA0
D_DDR3_BA1
D_DDR3_BA2
D_DDR3_DQS2
D_DDR3_DQS2B
D_DDR3_DQ23
D_DDR3_DQ22
D_DDR3_DQ19
D_DDR3_DQ18
D_DDR3_DQ16
D_DDR3_DQ21
D_DDR3_DQ20
D_DDR3_DQ17
D_DDR3_DM2
D_DDR3_DQ15
D_DDR3_DQ14
D_DDR3_DQ9
D_DDR3_DQ8
D_DDR3_DQ11
D_DDR3_DQ10
D_DDR3_DQ13
D_DDR3_DQ12
D_DDR3_DM1
D_DDR3_DQS1B
D_DDR3_DQS1
D_DDR3_DQ3
D_DDR3_DQ2
D_DDR3_DQ5
D_DDR3_DQ4
D_DDR3_DQ0
D_DDR3_DQ7
D_DDR3_DQ6
D_DDR3_DQ1
D_DDR3_DM0
D_DDR3_DQS0B
D_DDR3_DQS0
D_DDR3_DM3
D_DDR3_DQS3
D_DDR3_DQS3B
D_DDR3_DQ27
D_DDR3_DQ26
D_DDR3_DQ28
D_DDR3_DQ31
D_DDR3_DQ30
D_DDR3_DQ24
D_DDR3_DQ25
D_DDR3_DQ29
AVDD_DDR1_S
AVDD_DDR1_S
+1.5V_DDR AVDD_DDR1_S
AVDD_DDR1_S
AVDD_DDR1_S
AVDD_DDR1_S AVDD_DDR1_S
+1.5V_DDR
+1.5V_DDR
+1.5V_DDR
AVDD_DDR1_S
AVDD_DDR1_S
AVDD_DDR1_S
AVDD_DDR1_S
Title
Size Document Number Rev
Date: Sheet of 18
MSD6586
Ver.B
DRAM
7
Custom
Thursday, May 11, 2017
Title
Size Document Number Rev
Date: Sheet of 18
MSD6586
Ver.B
DRAM
7
Custom
Thursday, May 11, 2017
Title
Size Document Number Rev
Date: Sheet of 18
MSD6586
Ver.B
DRAM
7
Custom
Thursday, May 11, 2017
C187
100n/16V
R132
1k
1%
R117
1k
1%
R111
240R
1%
C181
100n/16V
C184
1n/50V
C177
100n/16V
R125
1k
1%
R126
1k
1%
MIU1
N1A
Macan_23x23_2L_DM_4
A-CKE
J27
A-RST
K27
DRAM_VREF
L26
ZQ
K26
ZQ1
M25
B-A0
E14
B-A1
B11
B-A2
D15
B-A3
D13
B-A4
B12
B-A5
E12
B-A6
A12
B-A7
F14
B-A8
E16
B-A9
C9
B-A10
B13
B-A11
D17
B-A12
F18
B-A13
A9
B-A14
A11
B-A15
F17
B-BA0
F13
B-BA1
F19
B-BA2
F12
B-RASZ
F16
B-CASZ
B10
B-WEZ
C10
B-ODT
F11
B-CKE
C14
B-RST
F15
B-MCLK
C15
B-MCLKZ
A14
B-CSB1
B8
B-CSB2
D11
B-DQ[0]
D23
B-DQ[1]
D19
B-DQ[2]
E22
B-DQ[3]
E18
B-DQ[4]
B21
B-DQ[5]
B15
B-DQ[6]
A21
B-DQ[7]
C16
B-DQM[0]
C17
B-DQS[0]
B19
B-DQSB[0]
C19
B-DQ[8]/DQU0
B17
B-DQ[9]/DQU1
E20
B-DQ[10]/DQU2
F20
B-DQ[11]/DQU3
B20
B-DQ[12]/DQU4
D21
B-DQ[13]/DQU5
F23
B-DQ[14]/DQU6
F21
B-DQ[15]/DQU7
F22
B-DQM[1]
A20
B-DQS[1]
A18
B-DQSB[1]
C18
B-DQ[16]/DQL0
B28
B-DQ[17]/DQL1
F24
B-DQ[18]/DQL2
C28
B-DQ[19]/DQL3
F25
B-DQ[20]/DQL4
F28
B-DQ[21]/DQL5
B22
B-DQ[22]/DQL6
E28
B-DQ[23]/DQL7
C23
B-DQM[2]
A23
B-DQS[2]
B26
B-DQSB[2]
C26
B-DQ[24]/DQU0
C24
B-DQ[25]/DQU1
F27
B-DQ[26]/DQU2
D25
B-DQ[27]/DQU3
C27
B-DQ[28]/DQU4
F26
B-DQ[29]/DQU5
E26
B-DQ[30]/DQU6
E24
B-DQ[31]/DQU7
D27
B-DQM[3]
A27
B-DQS[3]
C25
B-DQSB[3]
B24
RN6
82R
1
2
3
4 5
6
7
8
C160
100n/16V
C185
10n/50V
R128
2k
1%
C191
100n/16V
C176
100n/16V
R113
56R
C172
100n/16V
C178
100n/16V
R114
2k
1%
N12
H5TQ4G63CFR-RDC
VDD_0
B2
NC_0
J1
VSS_0
A9
VSSQ_0
B1
UDQS#_4
B7
VDDQ_0
A1
DQ14
B8
VSSQ_1
B9
UDM
D3
UDQS
C7
VSSQ_2
D1
DQ15
A3
VDDQ_1
A8
DQ9
C3
VDDQ_2
C1
VDDQ_3
C9
DQ8
D7
VDDQ_4
D2
DQ12
A7
VSSQ_3
D8
DQ11
C2
DQ10
C8
VSSQ_4
E2
DQ13
A2
VDD_1
D9
NC_1
J9
VSS_1
B3
VSSQ_5
E8
LDQS#_28
G3
VDDQ_5
E9
DQ6
G2
VSSQ_6
F9
LDM
E7
LDQS
F3
VSSQ_7
G1
DQ7
H7
VDDQ_6
F1
DQ1
F7
VDDQ_7
H2
DQ0
E3
VDDQ_8
H9
DQ4
H3
VSSQ_8
G9
DQ3
F8
DQ2
F2
BA2
M3
DQ5
H8
VDD_5
N1
VREFDQ
H1
VSS_2
E1
VSS_5
J8
CK
J7
VDD_2
G7
CKE
K9
WE#_54
L3
RAS#_55
J3
CK#_56
K7
ODT
K1
RESET#_58
T2
BA0
M2
BA1
N8
CAS#_61
K3
CS#_62
L2
A10_AP_63
L7
A1
P7
A2
P3
A0
N3
VDD_3
K2
VSS_3
G8
A3
N2
A5
P2
A6
R8
A4
P8
A7
R2
A9
R3
A11
R7
A8
T8
VSS_4
J2
VDD_4
K8
A12_BC#_79
N7
NC_3
L9
ZQ
L8
NC_2
L1
VREFCA
M8
NC_4
M7
A13
T3
A14
T7
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VDD_6
N9
VDD_7
R1
VDD_8
R9
R112
56R
C153
10n/50V
C168
100n/16V
C154
10u/10V
R133
1k
1%
C192
100n/16V
C167
1n/50V
N13
H5TQ4G63CFR-RDC
VDD_0
B2
NC_0
J1
VSS_0
A9
VSSQ_0
B1
UDQS#_4
B7
VDDQ_0
A1
DQ14
B8
VSSQ_1
B9
UDM
D3
UDQS
C7
VSSQ_2
D1
DQ15
A3
VDDQ_1
A8
DQ9
C3
VDDQ_2
C1
VDDQ_3
C9
DQ8
D7
VDDQ_4
D2
DQ12
A7
VSSQ_3
D8
DQ11
C2
DQ10
C8
VSSQ_4
E2
DQ13
A2
VDD_1
D9
NC_1
J9
VSS_1
B3
VSSQ_5
E8
LDQS#_28
G3
VDDQ_5
E9
DQ6
G2
VSSQ_6
F9
LDM
E7
LDQS
F3
VSSQ_7
G1
DQ7
H7
VDDQ_6
F1
DQ1
F7
VDDQ_7
H2
DQ0
E3
VDDQ_8
H9
DQ4
H3
VSSQ_8
G9
DQ3
F8
DQ2
F2
BA2
M3
DQ5
H8
VDD_5
N1
VREFDQ
H1
VSS_2
E1
VSS_5
J8
CK
J7
VDD_2
G7
CKE
K9
WE#_54
L3
RAS#_55
J3
CK#_56
K7
ODT
K1
RESET#_58
T2
BA0
M2
BA1
N8
CAS#_61
K3
CS#_62
L2
A10_AP_63
L7
A1
P7
A2
P3
A0
N3
VDD_3
K2
VSS_3
G8
A3
N2
A5
P2
A6
R8
A4
P8
A7
R2
A9
R3
A11
R7
A8
T8
VSS_4
J2
VDD_4
K8
A12_BC#_79
N7
NC_3
L9
ZQ
L8
NC_2
L1
VREFCA
M8
NC_4
M7
A13
T3
A14
T7
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VDD_6
N9
VDD_7
R1
VDD_8
R9
C159
100n/16V
RN8
82R
1
2
3
4 5
6
7
8
RN4
82R
1
2
3
4 5
6
7
8
C152
100n/16V
R122
56R
C155
10u/10V
R119
240R
1%
C190
100n/16V
R135
2k
1%
RN12
82R
1
2
3
4 5
6
7
8
R120
240R
1%
C180
100n/16V
C169
1n/50V
RN2
33R
1 8
2
3
4 5
7
6
C183
100n/16V
R115
2k
1%
C157
100n/16V
R131
1k
1%
C186
10n/50V
C197
100n/16V
C164
100n/16V
RN9
82R
1
2
3
4 5
6
7
8
C151
1n/50V
RN1
33R
1 8
2
3
4 5
7
6
C195
100n/16V
R118
240R
1%
RN3
82R
1
2
3
4 5
6
7
8
C196
100n/16V
C189
100n/16V
C194
100n/16V
C156
100n/16V
C173
100n/16V
C166
100n/16V
C165
100n/16V
C161
100n/16V
R121
56R
C158
100n/16V
R123
1k
1%
C175
100n/16V
R134
1k
1%
RN7
82R
1
2
3
4 5
6
7
8
C162
100n/16V
C182
100n/16V
C150
10n/50V/NC
R127
470R
C171
100n/16V
RN14
82R
1
2
3
4 5
6
7
8
R136
2k
1%
RN13
82R
1
2
3
4 5
6
7
8
C188
1n/50V
C149
10n/50V
R129
2k
1%
C193
100n/16V
C170
100n/16V
RN11
82R
1
2
3
4 5
6
7
8
R124
1k
1%
R116
1k
1%
C179
100n/16V
C199
100n/16V
C200
100n/16V
RN5
82R
1
2
3
4 5
6
7
8
R130
470R
C198
100n/16V
RN10
82R
1
2
3
4 5
6
7
8
C174
100n/16V
C163
100n/16V
Main board 7000 Circuit