Interrupt Control Register - INTC
This 8-bit register, known as the INTC register, controls the operation of both external and internal
interrupts. By setting various bits within this register using standard bit manipulation instructions,
the enable/disable function of the external interrupt and each of the internal interrupts can be inde
-
pendently controlled. A master interrupt bit within this register, the EMI bit, acts like a global en
-
able/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an
interrupt routine is entered to disable further interrupt and is set by the executing ²RETI² instruc
-
tion.
Note
In situations where other interrupts may require servicing within present interrupt service routines,
the EMI bit can be manually set by the program after the present interrupt service routine has been
entered.
Timer/Event Counter Registers
All devices possess a single internal 8-bit count-up timer, known as TMR, whose internal clock
source originates from the system clock f
SYS
. The PC1/TMR input pin is provided to allow the timer
to be used to count external events, measure time intervals and pulse widths. The timer can also
be used to generate accurate time bases or PFD signals. To control the action of the timer two spe
-
cial function registers are provided known as TMR and TMRC. The TMR register stores the actual
timer count-up value while the TMRC register is used to setup the various functions and options of
the timer. The TMR register can be preloaded with fixed data to allow different time intervals to be
programmed. The counter will begin counting from this preloaded value until full after which an in
-
ternal interrupt signal is generated and the TMR register then automatically re-loaded with its
preload value.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O registers and their associated control regis-
ters play a prominent role. All I/O ports have a designated register correspondingly labeled as PA,
PB and PC. These labeled I/O registers are mapped to specific addresses within the Data Memory
as shown in the Data Memory table which are used to transfer the appropriate output or input data
on that port. With each I/O port there is an associated control register labeled PAC, PBC and PCC,
also mapped to specific addresses with the Data Memory. The control register specifies which
pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corre
-
sponding bit of the control register must be set high, for an output it must be set low. During pro
-
gram initialization, it is important to first setup the control registers to specify which pins are
outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible
feature of these registers is the ability to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice-versa by ma
-
nipulating specific bits of the I/O control registers during normal program operation is a useful fea
-
ture of these devices.
22
Cost-Effective I/O Type MCU
To Next Page
Loading...