Using this method of frequency generation, and if a crystal oscillator is used for the system clock,
very precise values of frequency can be generated.
Prescaler
Bits 0~2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of
the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate sig
-
nals for buzzer driving and Timer Interrupt.
I/O Interfacing
The Timer/Event Counter when configured to run in the event counter or pulse width measure-
ment mode, require the use of external pin PC1/TMR for correct operation. The PC1/TMR pin is
pin-shared with other I/O pins, so the correct configuration option must be selected if this pin is to
be configured as a timer input pin. Pull-high resistors can be selected for connection to the timer in-
put pins. The timer can also be setup to drive the pin-shared buzzer pins. When the buzzer pins
are selected by selecting the correct configuration option, the output of the timer can be made to
drive this at a frequency determined by the contents of the timer prescaler and the timer TMR regis-
ter.
Programming Considerations
When configured to run in the timer mode, the internal system clock is used as the timer clock
source and is therefore synchronized with the overall operation of the microcontroller. In this
mode, when the appropriate timer register is full, the microcontroller will generate an internal inter
-
rupt signal directing the program flow to the respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also used as the timer clock source but the timer
will only run when the correct logic condition appears on the timer input pin PC1/TMR. As this is an
external event and not synchronized with the internal timer clock, the microcontroller will only see
this external event when the next timer clock pulse arrives. As a result there may be small differ
-
ences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the event counting mode which again is an ex
-
ternal event and not synchronized with the internal system or timer clock.
Chapter 1 Hardware Structure
31
T i m e r O v e r f l o w
B u z z e r C l o c k
P B 0 D a t a
B Z O u t p u t a t P B 0
B Z O u t p u t a t P B 1
PFD Output Control
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