Chapter 1 Hardware Structure
25
V
D D
M
U
X
C o n t r o l B i t
P u l l - H i g h O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
W e a k
P u l l - u p
D
Q
C K
Q
S
D
Q
C K
Q
S
P B 2
P B 3 ~ P B 7
( H T 4 8 R 0 7 A - 1 / H T 4 8 C 0 7 ,
H T 4 8 R 0 9 A - 1 / H T 4 8 C 0 9 )
P C 0 / I N T
P C 1 / T M R
P C 2
( H T 4 8 R 0 7 A - 1 / H T 4 8 C 0 7 ,
H T 4 8 R 0 9 A - 1 / H T 4 8 C 0 9 )
R e a d D a t a R e g i s t e r
I N T ( P C 0 o n l y )
T M R ( P C 1 o n l y )
PB2~PB7, PC0~PC2 Input/Output Ports
V
D D
M
U
X
M
U
X
R e a d D a t a R e g i s t e r
C o n t r o l B i t
P u l l - H i g h O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P B 0 D a t a B i t
B Z ( P B 1 o n l y )
B Z ( P B 0 o n l y )
B Z O p t i o n
P B 0 / B Z
P B 1 / B Z
W e a k
P u l l - u p
D
Q
C K
Q
S
D
Q
C K
Q
S
PB0~PB1 Input/Output Ports