Under normal program operation, the WDT time-out will initialize a ²chip reset² and set the status
bit ²TO². However, if the system is in the Power Down Mode, only a WDT time-out reset from
²HALT² will be initialized which will only reset the Program Counter and Stack Pointer. Three meth
-
ods can be adopted to clear the contents of the WDT including the WDT prescaler. The first is an
external hardware reset (a low level on the RES
pin), the second is via software instructions and
the third is via a ²HALT² instruction. There are two methods of using software instructions to clear
the Watchdog Timer, one of which must be chosen by configuration option. The first option is to
use the single ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1²
and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the WDT while
for the second option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully
clear the WDT. Note that for this second option, if ²CLR WDT1² is used to clear the WDT, succes-
sive executions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruc-
tion will clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a
successive ²CLR WDT1² instruction can clear the Watchdog Timer.
42
Cost-Effective I/O Type MCU
f S Y S / 4
8 - b i t C o u n t e r
(
¸
2 5 6 )
7 - b i t P r e s c a l e r
8 - t o - 1 M U X
W D T T i m e - o u t
W S 0 ~ W S 2
C o n f i g .
O p t i o n
S e l e c t
W D T O S C O u t p u t
W D T S o u r c e S e l e c t
C o n t r o l
L o g i c
C L R W D T 1 F l a g
C L R W D T 2 F l a g
1 o r 2 I n s t r u c t i o n s
C L R
C L R
Watchdog Timer
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