for increased memory performance, memory must be expanded two DIMM modules at a time. HP
offers option kits for expanding system memory.
Advanced memory protection
Advanced Error Checking and Correcting (ECC) memory functionality is standard on all ProLiant
DL560 servers. Advanced ECC technology detects and corrects single-bit and specific multi-bit errors
(4-bit and 8-bit errors occurring on a single DRAM chip on a DIMM).
As an option, HP Advanced Memory Protection is available for the ProLiant DL560 server. Advanced
Memory Protection is designed to maintain server availability and memory reliability without service
intervention. The ProLiant DL560 server includes support for OS-independent online spare memory: If
the number of single-bit correctable errors on a memory bank exceeds the pre-defined error threshold,
that bank will fail over to the online spare bank without intervention or server interruption. Online
spare memory can be configured across one or two memory cards. The failed memory can then be
replaced at the user’s convenience during a scheduled maintenance window.
All HP Advanced Memory Protection options are user configurable through the ROM-Based Setup
Utility and are viewable through Insight Manager 7 and the Integrated Management Log.
2-way interleaved memory
The ProLiant DL560 server uses two-way interleaving to improve memory performance. Two-way
interleaving works by dividing memory into multiple 64-bit blocks that can be accessed two at a time,
thus doubling the amount of data obtained in a single memory access from 64 bits to 128 bits and
reducing the required number of memory accesses. Reducing the number of memory accesses also
reduces the number of wait states, which further improves performance.
When the processor writes data to memory, the memory controller distributes, or interleaves, the data
across two DIMMs in a particular memory bank. When the processor requests a cache line of data,
the memory controller retrieves 32-bit blocks of data from both DIMMs in the addressed bank.
In addition to the requested data, the controller retrieves data from subsequent sequential memory
addresses on both DIMMs in anticipation of future data requests. The retrieved blocks of data are
merged together in 128-bit lines on the memory bus. The data is sent to the L2 cache as four 128-bit
lines (512 bits) to match the cache line size in the Intel Xeon Processor. The data rate on the memory
bus matches the data rate on the quad-pumped processor bus (3.2 GB/s), which reduces latency in
memory reads and writes.
Dual-interleaved memory fills the processor cache faster than standard, non-interleaved memory
systems so that the processors can execute applications faster. This synergy between the processor
and memory subsystems boosts the overall system performance of the ProLiant DL560 server well
beyond that of 2P or 4P servers without Hyper-Threading technology and two-way memory
interleaving. In fact, system performance truly scales with the number of processors: depending on
the application, a ProLiant DL560 server fully configured with four processors may outperform two
dual-processor servers.
I/O subsystem
The ServerWorks GC-LE chipset ensures that the bandwidth of the I/O subsystem complements the
processor and memory bandwidths. The chipset supports I/O bandwidth of 6.4 GB/s across two Inter
Module Buses (IMBs), supporting up to four independent PCI-X buses.
In the ProLiant DL560 server (Figure 2), IMB1 connects two embedded NC7781 10/100/1000 Port
PCI-X gigabit network interface controllers (NICs) and an integrated Smart Array 5i Plus storage
controller that supports two Ultra2 or Ultra3 SCSI internal disk drives or one disk drive and an internal
tape device. This storage controller supports the simplex drive cage and Dual Channel, Wide Ultra3
technology; but the ProLiant DL560 server uses only one channel. The storage controller supports up
to 64 MB of read cache on the 5i Plus Memory Module. With the addition of an optional write cache
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