IBM 5150 - Page 230

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Processor Control (Continued)

FLDENV = Load Enviroment

Escape 0 0 1

I mod 1 0 0 rIm

disp-Iow

disp-high

FSAVE = Save State

Escape 1 0 1

mod

1 1 0 rIm

disp-Iow

disp-high

FRSTOR = Restore State

Escape 1 0 1

I mod 1 0 0 rIm

disp-Iow

disp-high

FINCSTP = Increment Stack Pointer

Escape 0 0 1

I 1 1 1 1 0 1 1 1

FDECSTP = Decrement Stack Pointer

Escape 0 0 1

1 1 1

101

1 0

FFREE

= Free ST(i)

Escape 0 0 1 1 0 0 0 ST(i)

FNOP = No Operation

Escape 0 0 1

I 1 0 1 0 0 0 0

FWAIT =

CPU

Wait

for

NDP

10011011

Instruction Set

6-23

Main Page

Table of Contents10
Section 1. System Board20
Description22
Microprocessor22
Data Flow Diagrams24
System Memory Map27
System Timers30
System Interrupts30
Rom32
Ram32
Dma32
Channel33
System Board Diagram35
1/0 Channel Diagram37
I/O Channel Diagram38
I/O Channel Description39
I/O Address Map43
Address Map43
Other Circuits44
Speaker Circuit44
Cassette Interface46
Cassette Circuit Block Diagrams47
8255A I/O Bit Map50
System-Board Switch Settings52
Specifications53
Card Specifications53
Logic Diagrams55
Section 2. Coprocessor66
Description68
Programming Interface68
Hardware Interface69
Section 3. Power Supply72
Description74
Input Requirements75
Outputs75
VDC Output75
Vac Output76
Overvoltage/Overcurrent Protection76
Primary (Input)76
Secondary (Output)76
Power Good Signal77
Power Supply Connectors and Pin Assignments77
Section 4. Keyboard80
Description82
Block Diagram83
Keyboard Diagrams84
Connector Specifications91
Keyboard Logic Diagram92
Section 5. System Bios94
System BIOS Usage96
Vectors with Special Meanings99
Other Read/Write Memory Usage101
BIOS Programming Hints106
Adapter Cards with System-Accessible ROM Modules106
Keyboard Encoding and Usage107
Encoding107
Extended Codes111
Shift States112
Special Handling113
Extended Functions114
Keyboard Usage115
BIOS Cassette Logic118
Software Algorithms - Interrupt Hex 15118
Cassette Write118
Cassette Read119
Data Record Architecture120
Error Recovery121
System BIOS Listing122
Quick Reference122
Section 6. Instruction Set208
8088 Register Model208
Operand Summary211
Second Instruction Byte Summary211
Memory Segmentation Model212
Use of Segment Override212
Arithmetic215
Logic217
String Manipulation218
Control Transfer219
8088 Conditional Transfer Operations222
Processor Control223
8087 Extensions to the 8088 Instruction Set224
Data Transfer224
Comparison226
Arithmetic226
Transcendental228
Constants228
Processor Control229
8088 Instruction Set Matrix232
Instruction Set Index234
Section7. Characters, Keystrokes, and Colors236
Establishing a Communications Link254
Glossary262
Bibliography298
Index300

IBM 5150 - Page 230

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