Three
of
the four DMA channels are available on the
I/O
bus and
support high-speed data transfers between
1/0 devices and
memory without microprocessor intervention. The fourth DMA
channel
is
programmed to refresh the system dynamic memory.
This is done by programming a channel of the timer/counter
device to periodically request a dummy DMA transfer. This
action creates a memory-read cycle, which
is
available to refresh
dynamic storage both on the system board and in the system
expansion slots. All DMA data transfers, except the refresh
channel, take five microprocessor clocks of 21O-ns,
or
1.05-p,s if
the microprocessor ready line
is
not deactivated. Refresh DMA
cycles take four clocks or 840-ns.
The three programmable timer/counter devices are used by the
system as follows: Channel 0
is
used as a general-purpose timer
providing a constant time base for implementing a time-of-day
clock; Channel I
is
used to time and request refresh cycles from
the
DMA
channel; and Channel 2
is
used to support the tone
generation for the speaker. Each channel has a minimum timing
resolution of 1.05-us.
Of the eight prioritized levels of interrupt, six are bussed to the
system expansion slots for use by feature cards. Two levels are
~
used on the system board. Level 0, the highest priority,
is
attached to Channel 0 of the timer/counter device and provides a
periodic interrupt for the time-of-day clock.
Levell
is
attached
to the keyboard adapter circuits and receives an interrupt for each
scan code sent by the keyboard. The non-maskable interrupt
(NMI) of the 8088
is
used to report memory parity errors.
1/0
Channel
The
I/O
channel
is
an extension of the 8088 microprocessor bus.
H is, however, demultiplexed, repowered, and enhanced by the
addition of interrupts and direct memory access (DMA)
functions.
~
The
I/O
channel contains an 8-bit bidirectional data bus, 20
address lines, 6 levels of interrupt, control lines for memory and
I/O
read
or
write, clock and timing lines, 3 channels of DMA
1-14
System Board